tree: https://github.com/Freescale/linux-fslc 5.4-2.3.x-imx head: a8a2b9ee4bec0b29d031324160b7f11af42a563a commit: 7c335a91f0f4c6a7d7d0f8931e1570025222a379 [12045/16543] MLK-20023 Move Busfreq support to OPTEE OS config: arm-allyesconfig (attached as .config) compiler: arm-linux-gnueabi-gcc (GCC) 9.3.0 reproduce (this is a W=1 build): wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross chmod +x ~/bin/make.cross # https://github.com/Freescale/linux-fslc/commit/7c335a91f0f4c6a7d7d0f8931e... git remote add freescale-fslc https://github.com/Freescale/linux-fslc git fetch --no-tags freescale-fslc 5.4-2.3.x-imx git checkout 7c335a91f0f4c6a7d7d0f8931e1570025222a379 # save the attached .config to linux build tree COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-9.3.0 make.cross ARCH=arm If you fix the issue, kindly add following tag as appropriate Reported-by: kernel test robot <lkp(a)intel.com&gt; All warnings (new ones prefixed by >>): 107 | int update_freq_optee(int ddr_rate) | ^~~~~~~~~~~~~~~~~ 278 | int init_freq_optee(struct platform_device *busfreq_pdev) | ^~~~~~~~~~~~~~~ vim +/update_freq_optee +107 arch/arm/mach-imx/busfreq_optee.c 98 99 /** 100 * @brief Request OPTEE OS to change the memory bus frequency 101 * to \a ddr_rate value 102 * 103 * @param[in] rate Bus Frequency 104 * 105 * @retval 0 Success 106 */ 108 { 109 struct arm_smccc_res res; 110 111 uint32_t me = 0; 112 uint32_t dll_off = 0; 113 int mode = get_bus_freq_mode(); 114 115 #ifdef CONFIG_SMP 116 uint32_t reg = 0; 117 uint32_t cpu = 0; 118 uint32_t online_cpus = 0; 119 uint32_t all_cpus = 0; 120 #endif 121 122 pr_debug("\nBusfreq DDR3 OPTEE set from %d to %d start...\n", 123 curr_ddr_rate, ddr_rate); 124 125 if (ddr_rate == curr_ddr_rate) 126 return 0; 127 128 if (cpu_is_imx6()) { 129 if ((mode == BUS_FREQ_LOW) || (mode == BUS_FREQ_AUDIO)) 130 dll_off = 1; 131 } 132 133 local_irq_disable(); 134 135 #ifdef CONFIG_SMP 136 me = smp_processor_id(); 137 138 /* Make sure all the online cores to be active */ 139 do { 140 all_cpus = 0; 141 142 for_each_online_cpu(cpu) 143 all_cpus |= (pSync->wfe_status[cpu] << cpu); 144 } while (all_cpus); 145 146 pSync->change_ongoing = 1; 147 dsb(); 148 149 for_each_online_cpu(cpu) { 150 if (cpu != me) { 151 online_cpus |= (1 << cpu); 152 /* Set the interrupt to be pending in the GIC. */ 153 reg = 1 << (irqs_for_wfe[cpu] % 32); 154 writel_relaxed(reg, gic_dist_base + GIC_DIST_PENDING_SET 155 + (irqs_for_wfe[cpu] / 32) * 4); 156 } 157 } 158 159 /* Wait for all active CPUs to be in WFE */ 160 do { 161 all_cpus = 0; 162 163 for_each_online_cpu(cpu) 164 all_cpus |= (pSync->wfe_status[cpu] << cpu); 165 } while (all_cpus != online_cpus); 166 167 #endif 168 169 /* Now we can change the DDR frequency. */ 170 /* Call the TEE SiP */ 171 arm_smccc_smc(OPTEE_SMC_FAST_CALL_SIP_VAL(IMX_SIP_BUSFREQ_CHANGE), 172 ddr_rate, dll_off, 0, 0, 0, 0, 0, &res); 173 174 curr_ddr_rate = ddr_rate; 175 176 #ifdef CONFIG_SMP 177 /* DDR frequency change is done */ 178 pSync->change_ongoing = 0; 179 dsb(); 180 181 /* wake up all the cores. */ 182 sev(); 183 #endif 184 185 local_irq_enable(); 186 187 pr_debug("Busfreq OPTEE set to %d done! cpu=%d\n", ddr_rate, me); 188 189 return 0; 190 } 191 192 static int init_freq_optee_smp(struct platform_device *busfreq_pdev) 193 { 194 struct device_node *node = 0; 195 struct device *dev = &busfreq_pdev->dev; 196 uint32_t cpu; 197 int err; 198 int irq; 199 struct irq_data *irq_data; 200 unsigned long wfe_iram_base; 201 202 if (cpu_is_imx6()) { 203 node = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-gic"); 204 if (!node) { 205 if (cpu_is_imx6q()) 206 pr_debug("failed to find imx6q-a9-gic device tree data!\n"); 207 208 return -EINVAL; 209 } 210 } else { 211 node = of_find_compatible_node(NULL, NULL, "arm,cortex-a7-gic"); 212 if (!node) { 213 pr_debug("failed to find imx7d-a7-gic device tree data!\n"); 214 return -EINVAL; 215 } 216 } 217 218 gic_dist_base = of_iomap(node, 0); 219 WARN(!gic_dist_base, "unable to map gic dist registers\n"); 220 221 irqs_for_wfe = devm_kzalloc(dev, sizeof(uint32_t) * num_present_cpus(), 222 GFP_KERNEL); 223 224 for_each_online_cpu(cpu) { 225 /* 226 * set up a reserved interrupt to get all 227 * the active cores into a WFE state 228 * before changing the DDR frequency. 229 */ 230 irq = platform_get_irq(busfreq_pdev, cpu); 231 232 if (cpu_is_imx6()) { 233 err = request_irq(irq, wait_in_wfe_irq, 234 IRQF_PERCPU, "mmdc_1", NULL); 235 } else { 236 err = request_irq(irq, wait_in_wfe_irq, 237 IRQF_PERCPU, "ddrc", NULL); 238 } 239 240 if (err) { 241 dev_err(dev, 242 "Busfreq:request_irq failed %d, err = %d\n", 243 irq, err); 244 return err; 245 } 246 247 err = irq_set_affinity(irq, cpumask_of(cpu)); 248 if (err) { 249 dev_err(dev, 250 "Busfreq: Cannot set irq affinity irq=%d,\n", 251 irq); 252 return err; 253 } 254 255 irq_data = irq_get_irq_data(irq); 256 irqs_for_wfe[cpu] = irq_data->hwirq + 32; 257 } 258 259 /* Store the variable used to communicate between cores */ 260 pSync = (void *)ddr_freq_change_iram_base; 261 262 memset(pSync, 0, sizeof(*pSync)); 263 264 wfe_iram_base = ddr_freq_change_iram_base + sizeof(*pSync); 265 266 if (wfe_iram_base & (FNCPY_ALIGN - 1)) 267 wfe_iram_base += FNCPY_ALIGN - 268 ((uintptr_t)wfe_iram_base % (FNCPY_ALIGN)); 269 270 wfe_change_freq = (void *)fncpy((void *)wfe_iram_base, 271 &imx_smp_wfe_optee, 272 ((&imx_smp_wfe_end -&imx_smp_wfe_start) *4)); 273 274 return 0; 275 276 } 277 279 { 280 int err = -EINVAL; 281 struct device *dev = &busfreq_pdev->dev; 282 283 if (num_present_cpus() <= 1) { 284 wfe_change_freq = NULL; 285 286 /* Allocate the cores synchronization variables (not used) */ 287 pSync = devm_kzalloc(dev, sizeof(*pSync), GFP_KERNEL); 288 289 if (pSync) 290 err = 0; 291 } else { 292 err = init_freq_optee_smp(busfreq_pdev); 293 } 294 295 if (err == 0) 296 curr_ddr_rate = ddr_normal_rate; 297 298 return err; 299 } 300 --- 0-DAY CI Kernel Test Service, Intel Corporation https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org