tree: git://anongit.freedesktop.org/drm/drm-intel for-linux-next head: 1c8ee8b92fb6ac9d5975147cc902e8c142eca338 commit: 84eac0c65940d9633247b0c8c826d4bcb7307351 [4/5] drm/i915/gt: Force pte cacheline to main memory config: x86_64-randconfig-a011-20200511 (attached as .config) compiler: clang version 11.0.0 (https://github.com/llvm/llvm-project 68a9356bdea69dbcec1233f8b1fab47e72fca991) reproduce: git checkout 84eac0c65940d9633247b0c8c826d4bcb7307351 # save the attached .config to linux build tree make ARCH=x86_64 If you fix the issue, kindly add following tag as appropriate Reported-by: kbuild test robot <lkp(a)intel.com&gt; All warnings (new ones prefixed by >>): static __always_inline inline void ^ include/linux/compiler_types.h:138:16: note: expanded from macro 'inline' #define inline inline __gnu_inline __inline_maybe_unused notrace ^ 1 warning generated. vim +/inline +392 drivers/gpu/drm/i915/gt/gen8_ppgtt.c 391 393 write_pte(gen8_pte_t *pte, const gen8_pte_t val) 394 { 395 /* Magic delays? Or can we refine these to flush all in one pass? */ 396 *pte = val; 397 wmb(); /* cpu to cache */ 398 clflush(pte); /* cache to memory */ 399 wmb(); /* visible to all */ 400 } 401 --- 0-DAY CI Kernel Test Service, Intel Corporation https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org