tree: https://github.com/intel/linux-intel-lts.git 5.4/yocto head: eeb611e5394c56d45c5cc8f7dc484c9f19e93143 commit: 2baf6e1cd6f179dd497cfc10294920e99bc3a66e [39/1142] dmaengine: dw-axi-dma: support slave dma mode config: x86_64-randconfig-a004-20210618 (attached as .config) compiler: clang version 13.0.0 (https://github.com/llvm/llvm-project 64720f57bea6a6bf033feef4a5751ab9c0c3b401) reproduce (this is a W=1 build): wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross chmod +x ~/bin/make.cross # install x86_64 cross compiling tool for clang build # apt-get install binutils-x86-64-linux-gnu # https://github.com/intel/linux-intel-lts/commit/2baf6e1cd6f179dd497cfc102... git remote add intel-linux-intel-lts https://github.com/intel/linux-intel-lts.git git fetch --no-tags intel-linux-intel-lts 5.4/yocto git checkout 2baf6e1cd6f179dd497cfc10294920e99bc3a66e # save the attached .config to linux build tree COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross ARCH=x86_64 If you fix the issue, kindly add following tag as appropriate Reported-by: kernel test robot <lkp(a)intel.com&gt; All warnings (new ones prefixed by >>): size_t total_len = 0; ^ drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c:112:13: warning: unused function 'axi_free_hw_channel' [-Wunused-function] static void axi_free_hw_channel(struct axi_dma_chip *chip, u32 hs_id) ^ 2 warnings generated. vim +/total_len +703 drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c 684 685 static struct dma_async_tx_descriptor * 686 dma_chan_prep_slave_sg(struct dma_chan *dchan, struct scatterlist *sgl, 687 unsigned int sg_len, 688 enum dma_transfer_direction direction, 689 unsigned long flags, void *context) 690 { 691 struct axi_dma_chan *chan = dchan_to_axi_dma_chan(dchan); 692 unsigned int data_width = BIT(chan->chip->dw->hdata->m_data_width); 693 struct axi_dma_desc *first = NULL, *prev = NULL; 694 size_t block_ts, max_block_ts; 695 struct scatterlist *sg; 696 u32 reg_width; 697 u32 mem_width; 698 dma_addr_t reg; 699 u32 reg_value; 700 u32 i; 701 u32 ctllo, ctlhi; 702 u32 offset; 704 u8 lms = 0; /* Select AXI0 master for LLI fetching */ 705 706 if (unlikely(!is_slave_direction(direction) || !sg_len)) 707 return NULL; 708 709 chan->direction = direction; 710 711 max_block_ts = chan->chip->dw->hdata->block_size[chan->id]; 712 713 axi_set_hw_channel(chan->chip, chan->hw_hs_num); 714 715 switch (direction) { 716 case DMA_MEM_TO_DEV: 717 reg_width = __ffs(chan->slave_config.dst_addr_width); 718 chan->reg_width = reg_width; 719 720 if (reg_width == DWAXIDMAC_TRANS_WIDTH_16) { 721 offset = DMAC_APB_HALFWORD_WR_CH_EN; 722 reg_value = axi_dma_apb_ioread32(chan->chip, offset); 723 reg_value |= 0x1 << chan->id; 724 axi_dma_apb_iowrite32(chan->chip, offset, reg_value); 725 } else if (reg_width == DWAXIDMAC_TRANS_WIDTH_8) { 726 offset = DMAC_APB_BYTE_WR_CH_EN; 727 reg_value = axi_dma_apb_ioread32(chan->chip, offset); 728 reg_value |= 0x1 << chan->id; 729 axi_dma_apb_iowrite32(chan->chip, offset, reg_value); 730 } 731 732 reg = chan->slave_config.dst_addr; 733 734 ctllo = axi_dma_prepare_ctllo(chan) | 735 reg_width << CH_CTL_L_DST_WIDTH_POS | 736 DWAXIDMAC_CH_CTL_L_NOINC << CH_CTL_L_DST_INC_POS | 737 DWAXIDMAC_CH_CTL_L_INC << CH_CTL_L_SRC_INC_POS; 738 739 for_each_sg(sgl, sg, sg_len, i) { 740 struct axi_dma_desc *desc; 741 size_t xfer_len; 742 u32 mem, len; 743 744 mem = sg_dma_address(sg); 745 len = sg_dma_len(sg); 746 747 mem_width = __ffs(data_width | mem | len); 748 if (mem_width > DWAXIDMAC_TRANS_WIDTH_32) 749 mem_width = DWAXIDMAC_TRANS_WIDTH_32; 750 751 xfer_len = len; 752 block_ts = xfer_len >> mem_width; 753 754 slave_sg_todev_fill_desc: 755 desc = axi_desc_get(chan); 756 if (unlikely(!desc)) 757 goto err_desc_get; 758 if (block_ts > max_block_ts) { 759 block_ts = max_block_ts; 760 xfer_len = max_block_ts << mem_width; 761 } 762 block_ts = xfer_len; /* Workaround */ 763 ctlhi = axi_dma_prepare_ctlhi(chan); 764 765 ctllo |= mem_width << CH_CTL_L_SRC_WIDTH_POS; 766 767 write_desc_sar(desc, mem); 768 write_desc_dar(desc, reg); 769 desc->lli.block_ts_lo = cpu_to_le32(block_ts - 1); 770 desc->lli.ctl_hi = cpu_to_le32(ctlhi); 771 desc->lli.ctl_lo = cpu_to_le32(ctllo); 772 773 set_desc_src_master(desc); 774 775 /* Manage transfer list (xfer_list) */ 776 if (!first) { 777 first = desc; 778 } else { 779 write_desc_llp(prev, desc->vd.tx.phys | lms); 780 list_add_tail(&desc->xfer_list, 781 &first->xfer_list); 782 } 783 prev = desc; 784 785 /* update the length and addresses */ 786 mem += xfer_len; 787 len -= xfer_len; 788 total_len += xfer_len; 789 790 if (len) 791 goto slave_sg_todev_fill_desc; 792 793 /* Set end-of-link to the last link descriptor */ 794 set_desc_last(desc); 795 } 796 break; 797 case DMA_DEV_TO_MEM: 798 reg_width = __ffs(chan->slave_config.src_addr_width); 799 chan->reg_width = reg_width; 800 reg = chan->slave_config.src_addr; 801 ctllo = axi_dma_prepare_ctllo_rx(chan) | 802 reg_width << CH_CTL_L_SRC_WIDTH_POS | 803 DWAXIDMAC_CH_CTL_L_INC << CH_CTL_L_DST_INC_POS | 804 DWAXIDMAC_CH_CTL_L_NOINC << CH_CTL_L_SRC_INC_POS; 805 806 for_each_sg(sgl, sg, sg_len, i) { 807 struct axi_dma_desc *desc; 808 size_t xfer_len; 809 u32 mem, len; 810 811 mem = sg_dma_address(sg); 812 len = sg_dma_len(sg); 813 814 slave_sg_fromdev_fill_desc: 815 desc = axi_desc_get(chan); 816 if (unlikely(!desc)) 817 goto err_desc_get; 818 819 xfer_len = len; 820 block_ts = xfer_len >> reg_width; 821 if (block_ts > max_block_ts) { 822 block_ts = max_block_ts; 823 xfer_len = max_block_ts << reg_width; 824 } 825 826 mem_width = __ffs(data_width | mem | xfer_len); 827 if (mem_width > DWAXIDMAC_TRANS_WIDTH_32) 828 mem_width = DWAXIDMAC_TRANS_WIDTH_32; 829 ctlhi = axi_dma_prepare_ctlhi_rx(chan); 830 ctllo |= mem_width << CH_CTL_L_DST_WIDTH_POS; 831 832 ctllo |= mem_width << CH_CTL_L_DST_WIDTH_POS; 833 834 write_desc_sar(desc, reg); 835 write_desc_dar(desc, mem); 836 desc->lli.block_ts_lo = cpu_to_le32(block_ts - 1); 837 desc->lli.ctl_hi = cpu_to_le32(ctlhi); 838 desc->lli.ctl_lo = cpu_to_le32(ctllo); 839 840 set_desc_src_master(desc); 841 842 /* Manage transfer list (xfer_list) */ 843 if (!first) { 844 first = desc; 845 } else { 846 write_desc_llp(prev, desc->vd.tx.phys | lms); 847 list_add_tail(&desc->xfer_list, 848 &first->xfer_list); 849 } 850 prev = desc; 851 852 /* update the length and addresses */ 853 mem += xfer_len; 854 len -= xfer_len; 855 total_len += xfer_len; 856 857 if (len) 858 goto slave_sg_fromdev_fill_desc; 859 860 /* Set end-of-link to the last link descriptor */ 861 set_desc_last(desc); 862 } 863 break; 864 default: 865 return NULL; 866 } 867 868 if (unlikely(!first)) 869 return NULL; 870 871 return vchan_tx_prep(&chan->vc, &first->vd, flags); 872 873 err_desc_get: 874 if (first) 875 axi_desc_put(first); 876 877 return NULL; 878 } 879 --- 0-DAY CI Kernel Test Service, Intel Corporation https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org