Hi Jeffrey, [FYI, it's a private test report for your RFC patch.] [auto build test WARNING on char-misc/char-misc-testing] [also build test WARNING on soc/for-next linus/master v5.7-rc6 next-20200519] [cannot apply to linux/master] [if your patch is applied to the wrong git tree, please drop us a note to help improve the system. BTW, we also suggest to use '--base' option to specify the base tree in git format-patch, please see https://stackoverflow.com/a/37406982] url: https://github.com/0day-ci/linux/commits/Jeffrey-Hugo/Qualcomm-Cloud-AI-1... base: https://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc.git 57c76221d5af648c8355a55c09b050c5d8d38189 config: x86_64-allmodconfig (attached as .config) reproduce: # apt-get install sparse # sparse version: v0.6.1-193-gb8fad4bc-dirty # save the attached .config to linux build tree make C=1 ARCH=x86_64 CF='-fdiagnostic-prefix -D__CHECK_ENDIAN__' If you fix the issue, kindly add following tag as appropriate Reported-by: kbuild test robot <lkp(a)intel.com&gt; sparse warnings: (new ones prefixed by >>) drivers/misc/qaic/qaic_data.c:596:20: sparse: sparse: cast to restricted __le32 drivers/misc/qaic/qaic_data.c:637:9: sparse: got restricted __le32 [usertype] drivers/misc/qaic/qaic_data.c:789:16: sparse: sparse: cast to restricted __le32 drivers/misc/qaic/qaic_data.c:790:16: sparse: sparse: cast to restricted __le32 drivers/misc/qaic/qaic_data.c:833:17: sparse: sparse: incorrect type in argument 1 (different base types) @@ expected unsigned int val @@ got restricted __le3unsigned int val @@ drivers/misc/qaic/qaic_data.c:833:17: sparse: expected unsigned int val drivers/misc/qaic/qaic_data.c:833:17: sparse: got restricted __le32 [usertype] vim +455 drivers/misc/qaic/qaic_data.c 448 449 static int encode_execute(struct qaic_device *qdev, struct mem_handle *mem, 450 struct qaic_execute *exec, u16 req_id) 451 { 452 u8 cmd = BULK_XFER; 453 __le64 db_addr = cpu_to_le64(exec->db_addr); 454 u8 db_len; 456 struct scatterlist *sg; 457 u64 dev_addr; 458 int presync_sem; 459 int i; 460 461 if (!mem->no_xfer) 462 cmd |= (exec->dir == DMA_TO_DEVICE ? INBOUND_XFER : 463 OUTBOUND_XFER); 464 466 467 if (exec->db_len && !IS_ALIGNED(exec->db_addr, exec->db_len / 8)) 468 return -EINVAL; 469 470 presync_sem = exec->sem0.presync + exec->sem1.presync + 471 exec->sem2.presync + exec->sem3.presync; 472 if (presync_sem > 1) 473 return -EINVAL; 474 475 presync_sem = exec->sem0.presync << 0 | exec->sem1.presync << 1 | 476 exec->sem2.presync << 2 | exec->sem3.presync << 3; 477 478 switch (exec->db_len) { 479 case 32: 480 db_len = BIT(7); 481 break; 482 case 16: 483 db_len = BIT(7) | 1; 484 break; 485 case 8: 486 db_len = BIT(7) | 2; 487 break; 488 case 0: 489 db_len = 0; /* doorbell is not active for this command */ 490 break; 491 default: 492 return -EINVAL; /* should never hit this */ 493 } 494 495 /* 496 * When we end up splitting up a single request (ie a mem handle) into 497 * multiple DMA requests, we have to manage the sync data carefully. 498 * There can only be one presync sem. That needs to be on every xfer 499 * so that the DMA engine doesn't transfer data before the receiver is 500 * ready. We only do the doorbell and postsync sems after the xfer. 501 * To guarantee previous xfers for the request are complete, we use a 502 * fence. 503 */ 504 dev_addr = exec->dev_addr; 505 for_each_sg(mem->sgt->sgl, sg, mem->nents, i) { 507 mem->reqs[i].cmd = cmd; 508 mem->reqs[i].src_addr = 509 cpu_to_le64(exec->dir == DMA_TO_DEVICE ? 510 sg_dma_address(sg) : dev_addr); 511 mem->reqs[i].dest_addr = 512 cpu_to_le64(exec->dir == DMA_TO_DEVICE ? 513 dev_addr : sg_dma_address(sg)); 514 mem->reqs[i].len = cpu_to_le32(sg_dma_len(sg)); 515 switch (presync_sem) { 516 case BIT(0): 517 mem->reqs[i].sem_cmd0 = cpu_to_le32( 518 ENCODE_SEM(exec->sem0.val, 519 exec->sem0.index, 520 exec->sem0.presync, 521 exec->sem0.cmd, 522 exec->sem0.flags)); 523 break; 524 case BIT(1): 525 mem->reqs[i].sem_cmd1 = cpu_to_le32( 526 ENCODE_SEM(exec->sem1.val, 527 exec->sem1.index, 528 exec->sem1.presync, 529 exec->sem1.cmd, 530 exec->sem1.flags)); 531 break; 532 case BIT(2): 533 mem->reqs[i].sem_cmd2 = cpu_to_le32( 534 ENCODE_SEM(exec->sem2.val, 535 exec->sem2.index, 536 exec->sem2.presync, 537 exec->sem2.cmd, 538 exec->sem2.flags)); 539 break; 540 case BIT(3): 541 mem->reqs[i].sem_cmd3 = cpu_to_le32( 542 ENCODE_SEM(exec->sem3.val, 543 exec->sem3.index, 544 exec->sem3.presync, 545 exec->sem3.cmd, 546 exec->sem3.flags)); 547 break; 548 } 549 dev_addr += sg_dma_len(sg); 550 } 551 /* add post transfer stuff to last segment */ 552 i--; 553 mem->reqs[i].cmd |= GEN_COMPLETION; 554 mem->reqs[i].db_addr = db_addr; 555 mem->reqs[i].db_len = db_len; 557 exec->sem0.flags |= (exec->dir == DMA_TO_DEVICE ? SEM_INSYNCFENCE : 558 SEM_OUTSYNCFENCE); 559 mem->reqs[i].sem_cmd0 = cpu_to_le32(ENCODE_SEM(exec->sem0.val, 560 exec->sem0.index, 561 exec->sem0.presync, 562 exec->sem0.cmd, 563 exec->sem0.flags)); 564 mem->reqs[i].sem_cmd1 = cpu_to_le32(ENCODE_SEM(exec->sem1.val, 565 exec->sem1.index, 566 exec->sem1.presync, 567 exec->sem1.cmd, 568 exec->sem1.flags)); 569 mem->reqs[i].sem_cmd2 = cpu_to_le32(ENCODE_SEM(exec->sem2.val, 570 exec->sem2.index, 571 exec->sem2.presync, 572 exec->sem2.cmd, 573 exec->sem2.flags)); 574 mem->reqs[i].sem_cmd3 = cpu_to_le32(ENCODE_SEM(exec->sem3.val, 575 exec->sem3.index, 576 exec->sem3.presync, 577 exec->sem3.cmd, 578 exec->sem3.flags)); 579 580 return 0; 581 } 582 583 static int commit_execute(struct qaic_device *qdev, struct mem_handle *mem, 584 u32 dbc_id) 585 { 586 /** 587 * Use _relaxed accessors because we don't need barriers. This is 588 * part of our critical path - the faster we can submit work to the 589 * device, the faster the device can generate our output. At this point 590 * we haven't accessed the device, so we don't need to sync with 591 * previous activity, and we just need both values back, but it really 592 * doesn't matter which comes back first. 593 */ 594 struct dma_bridge_chan *dbc = &qdev->dbc[dbc_id]; 596 u32 tail = le32_to_cpu(readl_relaxed(dbc->dbc_base + REQTP_OFF)); 597 u32 avail = head - tail; 598 struct dbc_req *reqs = mem->reqs; 599 bool two_copy = tail + mem->nents > dbc->nelem; 600 601 if (head == U32_MAX || tail == U32_MAX) 602 /* PCI link error */ 603 return -ENODEV; 604 605 if (head <= tail) 606 avail += dbc->nelem; 607 608 --avail; 609 610 if (avail < mem->nents) 611 return -EAGAIN; 612 613 if (two_copy) { 614 avail = dbc->nelem - tail; 615 avail = min_t(u32, avail, mem->nents); 616 memcpy(dbc->req_q_base + tail * get_dbc_req_elem_size(), 617 reqs, sizeof(*reqs) * avail); 618 reqs += avail; 619 avail = mem->nents - avail; 620 if (avail) 621 memcpy(dbc->req_q_base, reqs, sizeof(*reqs) * avail); 622 } else { 623 memcpy(dbc->req_q_base + tail * get_dbc_req_elem_size(), 624 reqs, sizeof(*reqs) * mem->nents); 625 } 626 627 init_completion(&mem->xfer_done); 628 list_add_tail(&mem->list, &dbc->xfer_list); 629 tail = (tail + mem->nents) % dbc->nelem; 630 /** 631 * Use _relaxed because this is a critical path and we don't need a 632 * barrier. The data going to the device is in DMA coherent memory, 633 * thus the flushing of that data to memory is already handled and 634 * we don't need additional wait before we kick the device to process 635 * the request we just queued. 636 */ 638 return 0; 639 } 640 --- 0-DAY CI Kernel Test Service, Intel Corporation https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org