Hi Pankaj, Thank you for the patch! Yet something to improve: [auto build test ERROR on net/master] [cannot apply to v5.4-rc3 next-20191010] [if your patch is applied to the wrong git tree, please drop us a note to help improve the system. BTW, we also suggest to use '--base' option to specify the base tree in git format-patch, please see https://stackoverflow.com/a/37406982] url: https://github.com/0day-ci/linux/commits/Pankaj-Sharma/can-m_can-add-supp... config: x86_64-fedora-25 (attached as .config) compiler: gcc-7 (Debian 7.4.0-13) 7.4.0 reproduce: # save the attached .config to linux build tree make ARCH=x86_64 If you fix the issue, kindly add following tag Reported-by: kbuild test robot <lkp(a)intel.com&gt; All errors (new ones prefixed by >>): drivers/net/can/m_can/m_can.c: In function 'm_can_chip_config': if (priv->can.ctrlmode & CAN_CTRLMODE_ONE_SHOT) ^~~~ pid drivers/net/can/m_can/m_can.c:1170:6: note: each undeclared identifier is reported only once for each function it appears in vim +1170 drivers/net/can/m_can/m_can.c 1075 1076 /* Configure M_CAN chip: 1077 * - set rx buffer/fifo element size 1078 * - configure rx fifo 1079 * - accept non-matching frame into fifo 0 1080 * - configure tx buffer 1081 * - >= v3.1.x: TX FIFO is used 1082 * - configure mode 1083 * - setup bittiming 1084 */ 1085 static void m_can_chip_config(struct net_device *dev) 1086 { 1087 struct m_can_classdev *cdev = netdev_priv(dev); 1088 u32 cccr, test; 1089 1090 m_can_config_endisable(cdev, true); 1091 1092 /* RX Buffer/FIFO Element Size 64 bytes data field */ 1093 m_can_write(cdev, M_CAN_RXESC, M_CAN_RXESC_64BYTES); 1094 1095 /* Accept Non-matching Frames Into FIFO 0 */ 1096 m_can_write(cdev, M_CAN_GFC, 0x0); 1097 1098 if (cdev->version == 30) { 1099 /* only support one Tx Buffer currently */ 1100 m_can_write(cdev, M_CAN_TXBC, (1 << TXBC_NDTB_SHIFT) | 1101 cdev->mcfg[MRAM_TXB].off); 1102 } else { 1103 /* TX FIFO is used for newer IP Core versions */ 1104 m_can_write(cdev, M_CAN_TXBC, 1105 (cdev->mcfg[MRAM_TXB].num << TXBC_TFQS_SHIFT) | 1106 (cdev->mcfg[MRAM_TXB].off)); 1107 } 1108 1109 /* support 64 bytes payload */ 1110 m_can_write(cdev, M_CAN_TXESC, TXESC_TBDS_64BYTES); 1111 1112 /* TX Event FIFO */ 1113 if (cdev->version == 30) { 1114 m_can_write(cdev, M_CAN_TXEFC, (1 << TXEFC_EFS_SHIFT) | 1115 cdev->mcfg[MRAM_TXE].off); 1116 } else { 1117 /* Full TX Event FIFO is used */ 1118 m_can_write(cdev, M_CAN_TXEFC, 1119 ((cdev->mcfg[MRAM_TXE].num << TXEFC_EFS_SHIFT) 1120 & TXEFC_EFS_MASK) | 1121 cdev->mcfg[MRAM_TXE].off); 1122 } 1123 1124 /* rx fifo configuration, blocking mode, fifo size 1 */ 1125 m_can_write(cdev, M_CAN_RXF0C, 1126 (cdev->mcfg[MRAM_RXF0].num << RXFC_FS_SHIFT) | 1127 cdev->mcfg[MRAM_RXF0].off); 1128 1129 m_can_write(cdev, M_CAN_RXF1C, 1130 (cdev->mcfg[MRAM_RXF1].num << RXFC_FS_SHIFT) | 1131 cdev->mcfg[MRAM_RXF1].off); 1132 1133 cccr = m_can_read(cdev, M_CAN_CCCR); 1134 test = m_can_read(cdev, M_CAN_TEST); 1135 test &= ~TEST_LBCK; 1136 if (cdev->version == 30) { 1137 /* Version 3.0.x */ 1138 1139 cccr &= ~(CCCR_TEST | CCCR_MON | CCCR_DAR | 1140 (CCCR_CMR_MASK << CCCR_CMR_SHIFT) | 1141 (CCCR_CME_MASK << CCCR_CME_SHIFT)); 1142 1143 if (cdev->can.ctrlmode & CAN_CTRLMODE_FD) 1144 cccr |= CCCR_CME_CANFD_BRS << CCCR_CME_SHIFT; 1145 1146 } else { 1147 /* Version 3.1.x or 3.2.x */ 1148 cccr &= ~(CCCR_TEST | CCCR_MON | CCCR_BRSE | CCCR_FDOE | 1149 CCCR_NISO | CCCR_DAR); 1150 1151 /* Only 3.2.x has NISO Bit implemented */ 1152 if (cdev->can.ctrlmode & CAN_CTRLMODE_FD_NON_ISO) 1153 cccr |= CCCR_NISO; 1154 1155 if (cdev->can.ctrlmode & CAN_CTRLMODE_FD) 1156 cccr |= (CCCR_BRSE | CCCR_FDOE); 1157 } 1158 1159 /* Loopback Mode */ 1160 if (cdev->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) { 1161 cccr |= CCCR_TEST | CCCR_MON; 1162 test |= TEST_LBCK; 1163 } 1164 1165 /* Enable Monitoring (all versions) */ 1166 if (cdev->can.ctrlmode & CAN_CTRLMODE_LISTENONLY) 1167 cccr |= CCCR_MON; 1168 1169 /* Disable Auto Retransmission (all versions) */ 1171 cccr |= CCCR_DAR; 1172 1173 /* Write config */ 1174 m_can_write(cdev, M_CAN_CCCR, cccr); 1175 m_can_write(cdev, M_CAN_TEST, test); 1176 1177 /* Enable interrupts */ 1178 m_can_write(cdev, M_CAN_IR, IR_ALL_INT); 1179 if (!(cdev->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING)) 1180 if (cdev->version == 30) 1181 m_can_write(cdev, M_CAN_IE, IR_ALL_INT & 1182 ~(IR_ERR_LEC_30X)); 1183 else 1184 m_can_write(cdev, M_CAN_IE, IR_ALL_INT & 1185 ~(IR_ERR_LEC_31X)); 1186 else 1187 m_can_write(cdev, M_CAN_IE, IR_ALL_INT); 1188 1189 /* route all interrupts to INT0 */ 1190 m_can_write(cdev, M_CAN_ILS, ILS_ALL_INT0); 1191 1192 /* set bittiming params */ 1193 m_can_set_bittiming(dev); 1194 1195 m_can_config_endisable(cdev, false); 1196 1197 if (cdev->ops->init) 1198 cdev->ops->init(cdev); 1199 } 1200 --- 0-DAY kernel test infrastructure Open Source Technology Center https://lists.01.org/pipermail/kbuild-all Intel Corporation