Hi Jason, First bad commit (maybe != root cause): tree: https://github.com/Freescale/linux-fslc 5.4-2.3.x-imx head: ed8f0b9dafc6dfcfccb4507a8ae71aa294b2088b commit: 5bb09de3044acf91e6f8c712c026d5a4bc53b563 [15241/20737] MLK-24874-1: include: uapi: fmd: fix the UAPI_HEADER_TEST/install failure config: powerpc-randconfig-r025-20210822 (attached as .config) compiler: clang version 14.0.0 (https://github.com/llvm/llvm-project 79b55e5038324e61a3abf4e6a9a949c473edd858) reproduce (this is a W=1 build): wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross chmod +x ~/bin/make.cross # install powerpc cross compiling tool for clang build # apt-get install binutils-powerpc64-linux-gnu # https://github.com/Freescale/linux-fslc/commit/5bb09de3044acf91e6f8c712c0... git remote add freescale-fslc https://github.com/Freescale/linux-fslc git fetch --no-tags freescale-fslc 5.4-2.3.x-imx git checkout 5bb09de3044acf91e6f8c712c026d5a4bc53b563 # save the attached .config to linux build tree mkdir build_dir COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross O=build_dir ARCH=powerpc SHELL=/bin/bash If you fix the issue, kindly add following tag as appropriate Reported-by: kernel test robot <lkp(a)intel.com&gt; All errors (new ones prefixed by >>): arch/powerpc/platforms/85xx/sleep.S: Assembler messages: clang-14: error: assembler command failed with exit code 1 (use -v to see invocation) -- In file included from arch/powerpc/platforms/85xx/mpc85xx_pm_ops.c:10: In file included from include/linux/kernel.h:11: In file included from include/linux/compiler.h:256: arch/powerpc/include/asm/barrier.h:47:9: error: '__lwsync' macro redefined [-Werror,-Wmacro-redefined] #define __lwsync() __asm__ __volatile__ (stringify_in_c(LWSYNC) : : :"memory") ^ <built-in>:310:9: note: previous definition is here #define __lwsync __builtin_ppc_lwsync ^ int __init mpc85xx_setup_pmc(void) ^ arch/powerpc/platforms/85xx/mpc85xx_pm_ops.c:85:1: note: declare 'static' if the function is not intended to be used outside of this translation unit int __init mpc85xx_setup_pmc(void) ^ static 2 errors generated. vim +551 arch/powerpc/platforms/85xx/sleep.S dc640f653a5d465 Ran Wang 2018-03-28 528 dc640f653a5d465 Ran Wang 2018-03-28 529 /* Establish a temporary 64MB 0->0 mapping in TLB1[1]. */ dc640f653a5d465 Ran Wang 2018-03-28 530 lis r4, 0x1001 dc640f653a5d465 Ran Wang 2018-03-28 531 mtspr SPRN_MAS0, r4 dc640f653a5d465 Ran Wang 2018-03-28 532 lis r4, 0xc000 dc640f653a5d465 Ran Wang 2018-03-28 533 ori r4, r4, 0x0800 dc640f653a5d465 Ran Wang 2018-03-28 534 mtspr SPRN_MAS1, r4 dc640f653a5d465 Ran Wang 2018-03-28 535 li r4, 0 dc640f653a5d465 Ran Wang 2018-03-28 536 mtspr SPRN_MAS2, r4 dc640f653a5d465 Ran Wang 2018-03-28 537 li r4, 0x0015 dc640f653a5d465 Ran Wang 2018-03-28 538 mtspr SPRN_MAS3, r4 dc640f653a5d465 Ran Wang 2018-03-28 539 li r4, 0 dc640f653a5d465 Ran Wang 2018-03-28 540 mtspr SPRN_MAS7, r4 dc640f653a5d465 Ran Wang 2018-03-28 541 isync dc640f653a5d465 Ran Wang 2018-03-28 542 tlbwe dc640f653a5d465 Ran Wang 2018-03-28 543 isync dc640f653a5d465 Ran Wang 2018-03-28 544 dc640f653a5d465 Ran Wang 2018-03-28 545 lis r3, (3f - PAGE_OFFSET)@h dc640f653a5d465 Ran Wang 2018-03-28 546 ori r3, r3, (3f - PAGE_OFFSET)@l dc640f653a5d465 Ran Wang 2018-03-28 547 mtctr r3 dc640f653a5d465 Ran Wang 2018-03-28 548 bctr dc640f653a5d465 Ran Wang 2018-03-28 549 dc640f653a5d465 Ran Wang 2018-03-28 550 /* Locate the resume vector in the last word of the current page. */ dc640f653a5d465 Ran Wang 2018-03-28 @551 . = mpc85xx_enter_deep_sleep + 0xffc dc640f653a5d465 Ran Wang 2018-03-28 552 mpc85xx_deep_resume: dc640f653a5d465 Ran Wang 2018-03-28 553 b 2b dc640f653a5d465 Ran Wang 2018-03-28 554 dc640f653a5d465 Ran Wang 2018-03-28 555 3: dc640f653a5d465 Ran Wang 2018-03-28 556 /* Restore the contents of TLB1[0]. It is assumed that it covers dc640f653a5d465 Ran Wang 2018-03-28 557 * the currently executing code and the sleep save area, and that dc640f653a5d465 Ran Wang 2018-03-28 558 * it does not alias our temporary mapping (which is at virtual zero). dc640f653a5d465 Ran Wang 2018-03-28 559 */ dc640f653a5d465 Ran Wang 2018-03-28 560 lis r3, (TLBCAM - PAGE_OFFSET)@h dc640f653a5d465 Ran Wang 2018-03-28 561 ori r3, r3, (TLBCAM - PAGE_OFFSET)@l dc640f653a5d465 Ran Wang 2018-03-28 562 dc640f653a5d465 Ran Wang 2018-03-28 563 lwz r4, 0(r3) dc640f653a5d465 Ran Wang 2018-03-28 564 lwz r5, 4(r3) dc640f653a5d465 Ran Wang 2018-03-28 565 lwz r6, 8(r3) dc640f653a5d465 Ran Wang 2018-03-28 566 lwz r7, 12(r3) dc640f653a5d465 Ran Wang 2018-03-28 567 lwz r8, 16(r3) dc640f653a5d465 Ran Wang 2018-03-28 568 dc640f653a5d465 Ran Wang 2018-03-28 569 mtspr SPRN_MAS0, r4 dc640f653a5d465 Ran Wang 2018-03-28 570 mtspr SPRN_MAS1, r5 dc640f653a5d465 Ran Wang 2018-03-28 571 mtspr SPRN_MAS2, r6 dc640f653a5d465 Ran Wang 2018-03-28 572 mtspr SPRN_MAS3, r7 dc640f653a5d465 Ran Wang 2018-03-28 573 mtspr SPRN_MAS7, r8 dc640f653a5d465 Ran Wang 2018-03-28 574 dc640f653a5d465 Ran Wang 2018-03-28 575 isync dc640f653a5d465 Ran Wang 2018-03-28 576 tlbwe dc640f653a5d465 Ran Wang 2018-03-28 577 isync dc640f653a5d465 Ran Wang 2018-03-28 578 dc640f653a5d465 Ran Wang 2018-03-28 579 /* Access the ccsrbase address with TLB1[0] */ dc640f653a5d465 Ran Wang 2018-03-28 580 lis r5, ccsrbase_low@ha dc640f653a5d465 Ran Wang 2018-03-28 581 lwz r4, ccsrbase_low@l(r5) dc640f653a5d465 Ran Wang 2018-03-28 582 lis r5, ccsrbase_high@ha dc640f653a5d465 Ran Wang 2018-03-28 583 lwz r3, ccsrbase_high@l(r5) dc640f653a5d465 Ran Wang 2018-03-28 584 dc640f653a5d465 Ran Wang 2018-03-28 585 /* Use TLB1[15] to map the CCSR at 0xf0000000 */ dc640f653a5d465 Ran Wang 2018-03-28 586 lis r5, 0x100f dc640f653a5d465 Ran Wang 2018-03-28 587 mtspr SPRN_MAS0, r5 dc640f653a5d465 Ran Wang 2018-03-28 588 lis r5, 0xc000 dc640f653a5d465 Ran Wang 2018-03-28 589 ori r5, r5, 0x0500 dc640f653a5d465 Ran Wang 2018-03-28 590 mtspr SPRN_MAS1, r5 dc640f653a5d465 Ran Wang 2018-03-28 591 lis r5, 0xf000 dc640f653a5d465 Ran Wang 2018-03-28 592 ori r5, r5, 0x000a dc640f653a5d465 Ran Wang 2018-03-28 593 mtspr SPRN_MAS2, r5 dc640f653a5d465 Ran Wang 2018-03-28 594 rlwinm r5, r4, 0, 0xfffff000 dc640f653a5d465 Ran Wang 2018-03-28 595 ori r5, r5, 0x0005 dc640f653a5d465 Ran Wang 2018-03-28 596 mtspr SPRN_MAS3, r5 dc640f653a5d465 Ran Wang 2018-03-28 597 mtspr SPRN_MAS7, r3 dc640f653a5d465 Ran Wang 2018-03-28 598 isync dc640f653a5d465 Ran Wang 2018-03-28 599 tlbwe dc640f653a5d465 Ran Wang 2018-03-28 600 isync dc640f653a5d465 Ran Wang 2018-03-28 601 dc640f653a5d465 Ran Wang 2018-03-28 602 lis r3, 0xf002 /* L2 cache controller at CCSR+0x20000 */ dc640f653a5d465 Ran Wang 2018-03-28 603 bl invalidate_enable_L2 dc640f653a5d465 Ran Wang 2018-03-28 604 dc640f653a5d465 Ran Wang 2018-03-28 605 /* Access the MEM(r10) with TLB1[0] */ dc640f653a5d465 Ran Wang 2018-03-28 606 lis r10, mpc85xx_sleep_save_area@h dc640f653a5d465 Ran Wang 2018-03-28 607 ori r10, r10, mpc85xx_sleep_save_area@l dc640f653a5d465 Ran Wang 2018-03-28 608 dc640f653a5d465 Ran Wang 2018-03-28 609 lis r3, 0xf000 dc640f653a5d465 Ran Wang 2018-03-28 610 lwz r4, SS_BPTR(r10) dc640f653a5d465 Ran Wang 2018-03-28 611 stw r4, 0x20(r3) /* restore BPTR */ dc640f653a5d465 Ran Wang 2018-03-28 612 dc640f653a5d465 Ran Wang 2018-03-28 613 /* Program shift running space to PAGE_OFFSET */ dc640f653a5d465 Ran Wang 2018-03-28 614 mfmsr r3 dc640f653a5d465 Ran Wang 2018-03-28 615 lis r4, 1f@h dc640f653a5d465 Ran Wang 2018-03-28 616 ori r4, r4, 1f@l dc640f653a5d465 Ran Wang 2018-03-28 617 dc640f653a5d465 Ran Wang 2018-03-28 618 mtsrr1 r3 dc640f653a5d465 Ran Wang 2018-03-28 619 mtsrr0 r4 dc640f653a5d465 Ran Wang 2018-03-28 620 rfi dc640f653a5d465 Ran Wang 2018-03-28 621 :::::: The code at line 551 was first introduced by commit :::::: dc640f653a5d465ab03598388a1931894fa07ff7 powerpc/pm: add sleep and deep sleep on QorIQ SoCs :::::: TO: Ran Wang <ran.wang_1(a)nxp.com&gt; :::::: CC: Dong Aisheng <aisheng.dong(a)nxp.com&gt; --- 0-DAY CI Kernel Test Service, Intel Corporation https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org