tree: https://github.com/intel/linux-intel-lts.git 4.9/yocto/base head: 2a51382b3fd2c499ef6a2229389aa5c06481d1cf commit: 122b301e0181c2677aa49fe56537f905e8282bc3 [2/9] Merge tag 'v4.9.214' into lts2016/yocto config: i386-randconfig-a013-20200917 (attached as .config) compiler: gcc-7 (Ubuntu 7.5.0-6ubuntu2) 7.5.0 reproduce (this is a W=1 build): git checkout 122b301e0181c2677aa49fe56537f905e8282bc3 # save the attached .config to linux build tree make W=1 ARCH=i386 If you fix the issue, kindly add following tag as appropriate Reported-by: kernel test robot <lkp(a)intel.com&gt; All errors (new ones prefixed by >>): drivers/gpu/drm/i915/intel_lrc.c: In function 'gen9_init_indirectctx_bb': struct drm_i915_private *dev_priv = engine->i915; ^~~~~~~~ arch/x86/include/asm/bitops.h: Assembler messages: arch/x86/include/asm/bitops.h:257: Warning: no instruction mnemonic suffix given and no register operands; using default for `btr' arch/x86/include/asm/bitops.h:211: Warning: no instruction mnemonic suffix given and no register operands; using default for `bts' cc1: all warnings being treated as errors # https://github.com/intel/linux-intel-lts/commit/122b301e0181c2677aa49fe56... git remote add intel-linux-intel-lts https://github.com/intel/linux-intel-lts.git git fetch --no-tags intel-linux-intel-lts 4.9/yocto/base git checkout 122b301e0181c2677aa49fe56537f905e8282bc3 vim +/dev_priv +1109 drivers/gpu/drm/i915/intel_lrc.c 17ee950df38b649 Arun Siluvery 2015-06-19 1102 0bc40be85f33ca1 Tvrtko Ursulin 2016-03-16 1103 static int gen9_init_indirectctx_bb(struct intel_engine_cs *engine, 0504cffc7b128dc Arun Siluvery 2015-07-14 1104 struct i915_wa_ctx_bb *wa_ctx, 6e5248b53fda0dc Daniel Vetter 2016-07-15 1105 uint32_t *batch, 0504cffc7b128dc Arun Siluvery 2015-07-14 1106 uint32_t *offset) 0504cffc7b128dc Arun Siluvery 2015-07-14 1107 { a4106a782d11d44 Arun Siluvery 2015-07-14 1108 int ret; 5e580523d9128a4 Dave Airlie 2016-07-26 @1109 struct drm_i915_private *dev_priv = engine->i915; 0504cffc7b128dc Arun Siluvery 2015-07-14 1110 uint32_t index = wa_ctx_start(wa_ctx, *offset, CACHELINE_DWORDS); 571233331e19102 Akeem G Abodunrin 2020-01-08 1111 u32 scratch_addr = 571233331e19102 Akeem G Abodunrin 2020-01-08 1112 i915_ggtt_offset(engine->scratch) + 2 * CACHELINE_BYTES; 0504cffc7b128dc Arun Siluvery 2015-07-14 1113 3cd8216a9dc0515 Ander Conselvan de Oliveira 2017-01-26 1114 /* WaFlushCoherentL3CacheLinesAtContextSwitch:skl,bxt,glk */ 0bc40be85f33ca1 Tvrtko Ursulin 2016-03-16 1115 ret = gen8_emit_flush_coherentl3_wa(engine, batch, index); a4106a782d11d44 Arun Siluvery 2015-07-14 1116 if (ret < 0) a4106a782d11d44 Arun Siluvery 2015-07-14 1117 return ret; a4106a782d11d44 Arun Siluvery 2015-07-14 1118 index = ret; a4106a782d11d44 Arun Siluvery 2015-07-14 1119 3cd8216a9dc0515 Ander Conselvan de Oliveira 2017-01-26 1120 /* WaDisableGatherAtSetShaderCommonSlice:skl,bxt,kbl,glk */ 873e8171aebe9e6 Mika Kuoppala 2016-07-20 1121 wa_ctx_emit(batch, index, MI_LOAD_REGISTER_IMM(1)); 873e8171aebe9e6 Mika Kuoppala 2016-07-20 1122 wa_ctx_emit_reg(batch, index, COMMON_SLICE_CHICKEN2); 873e8171aebe9e6 Mika Kuoppala 2016-07-20 1123 wa_ctx_emit(batch, index, _MASKED_BIT_DISABLE( 873e8171aebe9e6 Mika Kuoppala 2016-07-20 1124 GEN9_DISABLE_GATHER_AT_SET_SHADER_COMMON_SLICE)); 873e8171aebe9e6 Mika Kuoppala 2016-07-20 1125 wa_ctx_emit(batch, index, MI_NOOP); 873e8171aebe9e6 Mika Kuoppala 2016-07-20 1126 571233331e19102 Akeem G Abodunrin 2020-01-08 1127 /* WaClearSlmSpaceAtContextSwitch:skl,bxt,kbl,glk,cfl */ 066d462888514af Mika Kuoppala 2016-06-07 1128 /* Actual scratch location is at 128 bytes offset */ 066d462888514af Mika Kuoppala 2016-06-07 1129 wa_ctx_emit(batch, index, GFX_OP_PIPE_CONTROL(6)); 066d462888514af Mika Kuoppala 2016-06-07 1130 wa_ctx_emit(batch, index, (PIPE_CONTROL_FLUSH_L3 | 066d462888514af Mika Kuoppala 2016-06-07 1131 PIPE_CONTROL_GLOBAL_GTT_IVB | 066d462888514af Mika Kuoppala 2016-06-07 1132 PIPE_CONTROL_CS_STALL | 066d462888514af Mika Kuoppala 2016-06-07 1133 PIPE_CONTROL_QW_WRITE)); 066d462888514af Mika Kuoppala 2016-06-07 1134 wa_ctx_emit(batch, index, scratch_addr); 066d462888514af Mika Kuoppala 2016-06-07 1135 wa_ctx_emit(batch, index, 0); 066d462888514af Mika Kuoppala 2016-06-07 1136 wa_ctx_emit(batch, index, 0); 066d462888514af Mika Kuoppala 2016-06-07 1137 wa_ctx_emit(batch, index, 0); 3485d99e415fade Tim Gore 2016-07-05 1138 3cd8216a9dc0515 Ander Conselvan de Oliveira 2017-01-26 1139 /* WaMediaPoolStateCmdInWABB:bxt,glk */ 3485d99e415fade Tim Gore 2016-07-05 1140 if (HAS_POOLED_EU(engine->i915)) { 3485d99e415fade Tim Gore 2016-07-05 1141 /* 3485d99e415fade Tim Gore 2016-07-05 1142 * EU pool configuration is setup along with golden context 3485d99e415fade Tim Gore 2016-07-05 1143 * during context initialization. This value depends on 3485d99e415fade Tim Gore 2016-07-05 1144 * device type (2x6 or 3x6) and needs to be updated based 3485d99e415fade Tim Gore 2016-07-05 1145 * on which subslice is disabled especially for 2x6 3485d99e415fade Tim Gore 2016-07-05 1146 * devices, however it is safe to load default 3485d99e415fade Tim Gore 2016-07-05 1147 * configuration of 3x6 device instead of masking off 3485d99e415fade Tim Gore 2016-07-05 1148 * corresponding bits because HW ignores bits of a disabled 3485d99e415fade Tim Gore 2016-07-05 1149 * subslice and drops down to appropriate config. Please 3485d99e415fade Tim Gore 2016-07-05 1150 * see render_state_setup() in i915_gem_render_state.c for 3485d99e415fade Tim Gore 2016-07-05 1151 * possible configurations, to avoid duplication they are 3485d99e415fade Tim Gore 2016-07-05 1152 * not shown here again. 3485d99e415fade Tim Gore 2016-07-05 1153 */ 3485d99e415fade Tim Gore 2016-07-05 1154 u32 eu_pool_config = 0x00777000; 3485d99e415fade Tim Gore 2016-07-05 1155 wa_ctx_emit(batch, index, GEN9_MEDIA_POOL_STATE); 3485d99e415fade Tim Gore 2016-07-05 1156 wa_ctx_emit(batch, index, GEN9_MEDIA_POOL_ENABLE); 3485d99e415fade Tim Gore 2016-07-05 1157 wa_ctx_emit(batch, index, eu_pool_config); 3485d99e415fade Tim Gore 2016-07-05 1158 wa_ctx_emit(batch, index, 0); 3485d99e415fade Tim Gore 2016-07-05 1159 wa_ctx_emit(batch, index, 0); 3485d99e415fade Tim Gore 2016-07-05 1160 wa_ctx_emit(batch, index, 0); 3485d99e415fade Tim Gore 2016-07-05 1161 } 3485d99e415fade Tim Gore 2016-07-05 1162 0504cffc7b128dc Arun Siluvery 2015-07-14 1163 /* Pad to end of cacheline */ 0504cffc7b128dc Arun Siluvery 2015-07-14 1164 while (index % CACHELINE_DWORDS) 0504cffc7b128dc Arun Siluvery 2015-07-14 1165 wa_ctx_emit(batch, index, MI_NOOP); 0504cffc7b128dc Arun Siluvery 2015-07-14 1166 0504cffc7b128dc Arun Siluvery 2015-07-14 1167 return wa_ctx_end(wa_ctx, *offset = index, CACHELINE_DWORDS); 0504cffc7b128dc Arun Siluvery 2015-07-14 1168 } 0504cffc7b128dc Arun Siluvery 2015-07-14 1169 :::::: The code at line 1109 was first introduced by commit :::::: 5e580523d9128a4d8364fe89d36c38fc7819c8dd Backmerge tag 'v4.7' into drm-next :::::: TO: Dave Airlie <airlied(a)redhat.com&gt; :::::: CC: Dave Airlie <airlied(a)redhat.com&gt; --- 0-DAY CI Kernel Test Service, Intel Corporation https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org