Hi Benjamin, I love your patch! Yet something to improve: [auto build test ERROR on sunxi/sunxi/for-next] [also build test ERROR on robh/for-next v5.12-rc3 next-20210317] [cannot apply to linuxtv-media/master] [If your patch is applied to the wrong git tree, kindly drop us a note. And when submitting patch, we suggest to use '--base' as documented in https://git-scm.com/docs/git-format-patch] url: https://github.com/0day-ci/linux/commits/Benjamin-Gaignard/Add-HANTRO-G2-... base: https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux.git sunxi/for-next config: nios2-allyesconfig (attached as .config) compiler: nios2-linux-gcc (GCC) 9.3.0 reproduce (this is a W=1 build): wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross chmod +x ~/bin/make.cross # https://github.com/0day-ci/linux/commit/8388a521cb8632e99a90afe38654f1810... git remote add linux-review https://github.com/0day-ci/linux git fetch --no-tags linux-review Benjamin-Gaignard/Add-HANTRO-G2-HEVC-decoder-support-for-IMX8MQ/20210318-013515 git checkout 8388a521cb8632e99a90afe38654f1810c60a549 # save the attached .config to linux build tree COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-9.3.0 make.cross ARCH=nios2 If you fix the issue, kindly add following tag as appropriate Reported-by: kernel test robot <lkp(a)intel.com&gt; All errors (new ones prefixed by >>): In file included from drivers/staging/media/sunxi/cedrus/cedrus_h265.c:17: drivers/staging/media/sunxi/cedrus/cedrus_h265.c: In function 'cedrus_h265_setup': 492 | VE_DEC_H265_DEC_SLICE_HDR_INFO1_SLICE_POC_BIGEST_IN_RPS_ST(decode_params->num_rps_poc_st_curr_after == 0) | | ^~~~~~~~~~~~~~~~~~~~~~~~~ drivers/staging/media/sunxi/cedrus/cedrus_regs.h:386:4: note: in definition of macro 'VE_DEC_H265_DEC_SLICE_HDR_INFO1_SLICE_POC_BIGEST_IN_RPS_ST' 386 | ((v) ? BIT(21) : 0) | ^ 532 | cedrus_h265_frame_info_write_dpb(ctx, slice_params->dpb, | ^~ drivers/staging/media/sunxi/cedrus/cedrus_h265.c:550:51: error: 'const struct v4l2_ctrl_hevc_slice_params' has no member named 'dpb' 550 | cedrus_h265_ref_pic_list_write(dev, slice_params->dpb, | ^~ drivers/staging/media/sunxi/cedrus/cedrus_h265.c:569:51: error: 'const struct v4l2_ctrl_hevc_slice_params' has no member named 'dpb' 569 | cedrus_h265_ref_pic_list_write(dev, slice_params->dpb, | ^~ vim +492 drivers/staging/media/sunxi/cedrus/cedrus_h265.c 240 241 static void cedrus_h265_setup(struct cedrus_ctx *ctx, 242 struct cedrus_run *run) 243 { 244 struct cedrus_dev *dev = ctx->dev; 245 const struct v4l2_ctrl_hevc_sps *sps; 246 const struct v4l2_ctrl_hevc_pps *pps; 247 const struct v4l2_ctrl_hevc_slice_params *slice_params; 248 const struct v4l2_ctrl_hevc_decode_params *decode_params; 249 const struct v4l2_hevc_pred_weight_table *pred_weight_table; 250 dma_addr_t src_buf_addr; 251 dma_addr_t src_buf_end_addr; 252 u32 chroma_log2_weight_denom; 253 u32 output_pic_list_index; 254 u32 pic_order_cnt[2]; 255 u32 reg; 256 257 sps = run->h265.sps; 258 pps = run->h265.pps; 259 slice_params = run->h265.slice_params; 260 decode_params = run->h265.decode_params; 261 pred_weight_table = &slice_params->pred_weight_table; 262 263 /* MV column buffer size and allocation. */ 264 if (!ctx->codec.h265.mv_col_buf_size) { 265 unsigned int num_buffers = 266 run->dst->vb2_buf.vb2_queue->num_buffers; 267 unsigned int log2_max_luma_coding_block_size = 268 sps->log2_min_luma_coding_block_size_minus3 + 3 + 269 sps->log2_diff_max_min_luma_coding_block_size; 270 unsigned int ctb_size_luma = 271 1UL << log2_max_luma_coding_block_size; 272 273 /* 274 * Each CTB requires a MV col buffer with a specific unit size. 275 * Since the address is given with missing lsb bits, 1 KiB is 276 * added to each buffer to ensure proper alignment. 277 */ 278 ctx->codec.h265.mv_col_buf_unit_size = 279 DIV_ROUND_UP(ctx->src_fmt.width, ctb_size_luma) * 280 DIV_ROUND_UP(ctx->src_fmt.height, ctb_size_luma) * 281 CEDRUS_H265_MV_COL_BUF_UNIT_CTB_SIZE + SZ_1K; 282 283 ctx->codec.h265.mv_col_buf_size = num_buffers * 284 ctx->codec.h265.mv_col_buf_unit_size; 285 286 ctx->codec.h265.mv_col_buf = 287 dma_alloc_coherent(dev->dev, 288 ctx->codec.h265.mv_col_buf_size, 289 &ctx->codec.h265.mv_col_buf_addr, 290 GFP_KERNEL); 291 if (!ctx->codec.h265.mv_col_buf) { 292 ctx->codec.h265.mv_col_buf_size = 0; 293 // TODO: Abort the process here. 294 return; 295 } 296 } 297 298 /* Activate H265 engine. */ 299 cedrus_engine_enable(ctx, CEDRUS_CODEC_H265); 300 301 /* Source offset and length in bits. */ 302 303 cedrus_write(dev, VE_DEC_H265_BITS_OFFSET, 0); 304 305 reg = slice_params->bit_size; 306 cedrus_write(dev, VE_DEC_H265_BITS_LEN, reg); 307 308 /* Source beginning and end addresses. */ 309 310 src_buf_addr = vb2_dma_contig_plane_dma_addr(&run->src->vb2_buf, 0); 311 312 reg = VE_DEC_H265_BITS_ADDR_BASE(src_buf_addr); 313 reg |= VE_DEC_H265_BITS_ADDR_VALID_SLICE_DATA; 314 reg |= VE_DEC_H265_BITS_ADDR_LAST_SLICE_DATA; 315 reg |= VE_DEC_H265_BITS_ADDR_FIRST_SLICE_DATA; 316 317 cedrus_write(dev, VE_DEC_H265_BITS_ADDR, reg); 318 319 src_buf_end_addr = src_buf_addr + 320 DIV_ROUND_UP(slice_params->bit_size, 8); 321 322 reg = VE_DEC_H265_BITS_END_ADDR_BASE(src_buf_end_addr); 323 cedrus_write(dev, VE_DEC_H265_BITS_END_ADDR, reg); 324 325 /* Coding tree block address: start at the beginning. */ 326 reg = VE_DEC_H265_DEC_CTB_ADDR_X(0) | VE_DEC_H265_DEC_CTB_ADDR_Y(0); 327 cedrus_write(dev, VE_DEC_H265_DEC_CTB_ADDR, reg); 328 329 cedrus_write(dev, VE_DEC_H265_TILE_START_CTB, 0); 330 cedrus_write(dev, VE_DEC_H265_TILE_END_CTB, 0); 331 332 /* Clear the number of correctly-decoded coding tree blocks. */ 333 cedrus_write(dev, VE_DEC_H265_DEC_CTB_NUM, 0); 334 335 /* Initialize bitstream access. */ 336 cedrus_write(dev, VE_DEC_H265_TRIGGER, VE_DEC_H265_TRIGGER_INIT_SWDEC); 337 338 cedrus_h265_skip_bits(dev, slice_params->data_bit_offset); 339 340 /* Bitstream parameters. */ 341 342 reg = VE_DEC_H265_DEC_NAL_HDR_NAL_UNIT_TYPE(slice_params->nal_unit_type) | 343 VE_DEC_H265_DEC_NAL_HDR_NUH_TEMPORAL_ID_PLUS1(slice_params->nuh_temporal_id_plus1); 344 345 cedrus_write(dev, VE_DEC_H265_DEC_NAL_HDR, reg); 346 347 /* SPS. */ 348 349 reg = VE_DEC_H265_DEC_SPS_HDR_MAX_TRANSFORM_HIERARCHY_DEPTH_INTRA(sps->max_transform_hierarchy_depth_intra) | 350 VE_DEC_H265_DEC_SPS_HDR_MAX_TRANSFORM_HIERARCHY_DEPTH_INTER(sps->max_transform_hierarchy_depth_inter) | 351 VE_DEC_H265_DEC_SPS_HDR_LOG2_DIFF_MAX_MIN_TRANSFORM_BLOCK_SIZE(sps->log2_diff_max_min_luma_transform_block_size) | 352 VE_DEC_H265_DEC_SPS_HDR_LOG2_MIN_TRANSFORM_BLOCK_SIZE_MINUS2(sps->log2_min_luma_transform_block_size_minus2) | 353 VE_DEC_H265_DEC_SPS_HDR_LOG2_DIFF_MAX_MIN_LUMA_CODING_BLOCK_SIZE(sps->log2_diff_max_min_luma_coding_block_size) | 354 VE_DEC_H265_DEC_SPS_HDR_LOG2_MIN_LUMA_CODING_BLOCK_SIZE_MINUS3(sps->log2_min_luma_coding_block_size_minus3) | 355 VE_DEC_H265_DEC_SPS_HDR_BIT_DEPTH_CHROMA_MINUS8(sps->bit_depth_chroma_minus8) | 356 VE_DEC_H265_DEC_SPS_HDR_BIT_DEPTH_LUMA_MINUS8(sps->bit_depth_luma_minus8) | 357 VE_DEC_H265_DEC_SPS_HDR_CHROMA_FORMAT_IDC(sps->chroma_format_idc); 358 359 reg |= VE_DEC_H265_FLAG(VE_DEC_H265_DEC_SPS_HDR_FLAG_STRONG_INTRA_SMOOTHING_ENABLE, 360 V4L2_HEVC_SPS_FLAG_STRONG_INTRA_SMOOTHING_ENABLED, 361 sps->flags); 362 363 reg |= VE_DEC_H265_FLAG(VE_DEC_H265_DEC_SPS_HDR_FLAG_SPS_TEMPORAL_MVP_ENABLED, 364 V4L2_HEVC_SPS_FLAG_SPS_TEMPORAL_MVP_ENABLED, 365 sps->flags); 366 367 reg |= VE_DEC_H265_FLAG(VE_DEC_H265_DEC_SPS_HDR_FLAG_SAMPLE_ADAPTIVE_OFFSET_ENABLED, 368 V4L2_HEVC_SPS_FLAG_SAMPLE_ADAPTIVE_OFFSET, 369 sps->flags); 370 371 reg |= VE_DEC_H265_FLAG(VE_DEC_H265_DEC_SPS_HDR_FLAG_AMP_ENABLED, 372 V4L2_HEVC_SPS_FLAG_AMP_ENABLED, sps->flags); 373 374 reg |= VE_DEC_H265_FLAG(VE_DEC_H265_DEC_SPS_HDR_FLAG_SEPARATE_COLOUR_PLANE, 375 V4L2_HEVC_SPS_FLAG_SEPARATE_COLOUR_PLANE, 376 sps->flags); 377 378 cedrus_write(dev, VE_DEC_H265_DEC_SPS_HDR, reg); 379 380 reg = VE_DEC_H265_DEC_PCM_CTRL_LOG2_DIFF_MAX_MIN_PCM_LUMA_CODING_BLOCK_SIZE(sps->log2_diff_max_min_pcm_luma_coding_block_size) | 381 VE_DEC_H265_DEC_PCM_CTRL_LOG2_MIN_PCM_LUMA_CODING_BLOCK_SIZE_MINUS3(sps->log2_min_pcm_luma_coding_block_size_minus3) | 382 VE_DEC_H265_DEC_PCM_CTRL_PCM_SAMPLE_BIT_DEPTH_CHROMA_MINUS1(sps->pcm_sample_bit_depth_chroma_minus1) | 383 VE_DEC_H265_DEC_PCM_CTRL_PCM_SAMPLE_BIT_DEPTH_LUMA_MINUS1(sps->pcm_sample_bit_depth_luma_minus1); 384 385 reg |= VE_DEC_H265_FLAG(VE_DEC_H265_DEC_PCM_CTRL_FLAG_PCM_ENABLED, 386 V4L2_HEVC_SPS_FLAG_PCM_ENABLED, sps->flags); 387 388 reg |= VE_DEC_H265_FLAG(VE_DEC_H265_DEC_PCM_CTRL_FLAG_PCM_LOOP_FILTER_DISABLED, 389 V4L2_HEVC_SPS_FLAG_PCM_LOOP_FILTER_DISABLED, 390 sps->flags); 391 392 cedrus_write(dev, VE_DEC_H265_DEC_PCM_CTRL, reg); 393 394 /* PPS. */ 395 396 reg = VE_DEC_H265_DEC_PPS_CTRL0_PPS_CR_QP_OFFSET(pps->pps_cr_qp_offset) | 397 VE_DEC_H265_DEC_PPS_CTRL0_PPS_CB_QP_OFFSET(pps->pps_cb_qp_offset) | 398 VE_DEC_H265_DEC_PPS_CTRL0_INIT_QP_MINUS26(pps->init_qp_minus26) | 399 VE_DEC_H265_DEC_PPS_CTRL0_DIFF_CU_QP_DELTA_DEPTH(pps->diff_cu_qp_delta_depth); 400 401 reg |= VE_DEC_H265_FLAG(VE_DEC_H265_DEC_PPS_CTRL0_FLAG_CU_QP_DELTA_ENABLED, 402 V4L2_HEVC_PPS_FLAG_CU_QP_DELTA_ENABLED, 403 pps->flags); 404 405 reg |= VE_DEC_H265_FLAG(VE_DEC_H265_DEC_PPS_CTRL0_FLAG_TRANSFORM_SKIP_ENABLED, 406 V4L2_HEVC_PPS_FLAG_TRANSFORM_SKIP_ENABLED, 407 pps->flags); 408 409 reg |= VE_DEC_H265_FLAG(VE_DEC_H265_DEC_PPS_CTRL0_FLAG_CONSTRAINED_INTRA_PRED, 410 V4L2_HEVC_PPS_FLAG_CONSTRAINED_INTRA_PRED, 411 pps->flags); 412 413 reg |= VE_DEC_H265_FLAG(VE_DEC_H265_DEC_PPS_CTRL0_FLAG_SIGN_DATA_HIDING_ENABLED, 414 V4L2_HEVC_PPS_FLAG_SIGN_DATA_HIDING_ENABLED, 415 pps->flags); 416 417 cedrus_write(dev, VE_DEC_H265_DEC_PPS_CTRL0, reg); 418 419 reg = VE_DEC_H265_DEC_PPS_CTRL1_LOG2_PARALLEL_MERGE_LEVEL_MINUS2(pps->log2_parallel_merge_level_minus2); 420 421 reg |= VE_DEC_H265_FLAG(VE_DEC_H265_DEC_PPS_CTRL1_FLAG_PPS_LOOP_FILTER_ACROSS_SLICES_ENABLED, 422 V4L2_HEVC_PPS_FLAG_PPS_LOOP_FILTER_ACROSS_SLICES_ENABLED, 423 pps->flags); 424 425 reg |= VE_DEC_H265_FLAG(VE_DEC_H265_DEC_PPS_CTRL1_FLAG_LOOP_FILTER_ACROSS_TILES_ENABLED, 426 V4L2_HEVC_PPS_FLAG_LOOP_FILTER_ACROSS_TILES_ENABLED, 427 pps->flags); 428 429 reg |= VE_DEC_H265_FLAG(VE_DEC_H265_DEC_PPS_CTRL1_FLAG_ENTROPY_CODING_SYNC_ENABLED, 430 V4L2_HEVC_PPS_FLAG_ENTROPY_CODING_SYNC_ENABLED, 431 pps->flags); 432 433 /* TODO: VE_DEC_H265_DEC_PPS_CTRL1_FLAG_TILES_ENABLED */ 434 435 reg |= VE_DEC_H265_FLAG(VE_DEC_H265_DEC_PPS_CTRL1_FLAG_TRANSQUANT_BYPASS_ENABLED, 436 V4L2_HEVC_PPS_FLAG_TRANSQUANT_BYPASS_ENABLED, 437 pps->flags); 438 439 reg |= VE_DEC_H265_FLAG(VE_DEC_H265_DEC_PPS_CTRL1_FLAG_WEIGHTED_BIPRED, 440 V4L2_HEVC_PPS_FLAG_WEIGHTED_BIPRED, pps->flags); 441 442 reg |= VE_DEC_H265_FLAG(VE_DEC_H265_DEC_PPS_CTRL1_FLAG_WEIGHTED_PRED, 443 V4L2_HEVC_PPS_FLAG_WEIGHTED_PRED, pps->flags); 444 445 cedrus_write(dev, VE_DEC_H265_DEC_PPS_CTRL1, reg); 446 447 /* Slice Parameters. */ 448 449 reg = VE_DEC_H265_DEC_SLICE_HDR_INFO0_PICTURE_TYPE(slice_params->pic_struct) | 450 VE_DEC_H265_DEC_SLICE_HDR_INFO0_FIVE_MINUS_MAX_NUM_MERGE_CAND(slice_params->five_minus_max_num_merge_cand) | 451 VE_DEC_H265_DEC_SLICE_HDR_INFO0_NUM_REF_IDX_L1_ACTIVE_MINUS1(slice_params->num_ref_idx_l1_active_minus1) | 452 VE_DEC_H265_DEC_SLICE_HDR_INFO0_NUM_REF_IDX_L0_ACTIVE_MINUS1(slice_params->num_ref_idx_l0_active_minus1) | 453 VE_DEC_H265_DEC_SLICE_HDR_INFO0_COLLOCATED_REF_IDX(slice_params->collocated_ref_idx) | 454 VE_DEC_H265_DEC_SLICE_HDR_INFO0_COLOUR_PLANE_ID(slice_params->colour_plane_id) | 455 VE_DEC_H265_DEC_SLICE_HDR_INFO0_SLICE_TYPE(slice_params->slice_type); 456 457 reg |= VE_DEC_H265_FLAG(VE_DEC_H265_DEC_SLICE_HDR_INFO0_FLAG_COLLOCATED_FROM_L0, 458 V4L2_HEVC_SLICE_PARAMS_FLAG_COLLOCATED_FROM_L0, 459 slice_params->flags); 460 461 reg |= VE_DEC_H265_FLAG(VE_DEC_H265_DEC_SLICE_HDR_INFO0_FLAG_CABAC_INIT, 462 V4L2_HEVC_SLICE_PARAMS_FLAG_CABAC_INIT, 463 slice_params->flags); 464 465 reg |= VE_DEC_H265_FLAG(VE_DEC_H265_DEC_SLICE_HDR_INFO0_FLAG_MVD_L1_ZERO, 466 V4L2_HEVC_SLICE_PARAMS_FLAG_MVD_L1_ZERO, 467 slice_params->flags); 468 469 reg |= VE_DEC_H265_FLAG(VE_DEC_H265_DEC_SLICE_HDR_INFO0_FLAG_SLICE_SAO_CHROMA, 470 V4L2_HEVC_SLICE_PARAMS_FLAG_SLICE_SAO_CHROMA, 471 slice_params->flags); 472 473 reg |= VE_DEC_H265_FLAG(VE_DEC_H265_DEC_SLICE_HDR_INFO0_FLAG_SLICE_SAO_LUMA, 474 V4L2_HEVC_SLICE_PARAMS_FLAG_SLICE_SAO_LUMA, 475 slice_params->flags); 476 477 reg |= VE_DEC_H265_FLAG(VE_DEC_H265_DEC_SLICE_HDR_INFO0_FLAG_SLICE_TEMPORAL_MVP_ENABLE, 478 V4L2_HEVC_SLICE_PARAMS_FLAG_SLICE_TEMPORAL_MVP_ENABLED, 479 slice_params->flags); 480 481 reg |= VE_DEC_H265_FLAG(VE_DEC_H265_DEC_SLICE_HDR_INFO0_FLAG_DEPENDENT_SLICE_SEGMENT, 482 V4L2_HEVC_PPS_FLAG_DEPENDENT_SLICE_SEGMENT, 483 pps->flags); 484 485 /* FIXME: For multi-slice support. */ 486 reg |= VE_DEC_H265_DEC_SLICE_HDR_INFO0_FLAG_FIRST_SLICE_SEGMENT_IN_PIC; 487 488 cedrus_write(dev, VE_DEC_H265_DEC_SLICE_HDR_INFO0, reg); 489 490 reg = VE_DEC_H265_DEC_SLICE_HDR_INFO1_SLICE_TC_OFFSET_DIV2(slice_params->slice_tc_offset_div2) | 491 VE_DEC_H265_DEC_SLICE_HDR_INFO1_SLICE_BETA_OFFSET_DIV2(slice_params->slice_beta_offset_div2) | 493 VE_DEC_H265_DEC_SLICE_HDR_INFO1_SLICE_CR_QP_OFFSET(slice_params->slice_cr_qp_offset) | 494 VE_DEC_H265_DEC_SLICE_HDR_INFO1_SLICE_CB_QP_OFFSET(slice_params->slice_cb_qp_offset) | 495 VE_DEC_H265_DEC_SLICE_HDR_INFO1_SLICE_QP_DELTA(slice_params->slice_qp_delta); 496 497 reg |= VE_DEC_H265_FLAG(VE_DEC_H265_DEC_SLICE_HDR_INFO1_FLAG_SLICE_DEBLOCKING_FILTER_DISABLED, 498 V4L2_HEVC_SLICE_PARAMS_FLAG_SLICE_DEBLOCKING_FILTER_DISABLED, 499 slice_params->flags); 500 501 reg |= VE_DEC_H265_FLAG(VE_DEC_H265_DEC_SLICE_HDR_INFO1_FLAG_SLICE_LOOP_FILTER_ACROSS_SLICES_ENABLED, 502 V4L2_HEVC_SLICE_PARAMS_FLAG_SLICE_LOOP_FILTER_ACROSS_SLICES_ENABLED, 503 slice_params->flags); 504 505 cedrus_write(dev, VE_DEC_H265_DEC_SLICE_HDR_INFO1, reg); 506 507 chroma_log2_weight_denom = pred_weight_table->luma_log2_weight_denom + 508 pred_weight_table->delta_chroma_log2_weight_denom; 509 reg = VE_DEC_H265_DEC_SLICE_HDR_INFO2_NUM_ENTRY_POINT_OFFSETS(0) | 510 VE_DEC_H265_DEC_SLICE_HDR_INFO2_CHROMA_LOG2_WEIGHT_DENOM(chroma_log2_weight_denom) | 511 VE_DEC_H265_DEC_SLICE_HDR_INFO2_LUMA_LOG2_WEIGHT_DENOM(pred_weight_table->luma_log2_weight_denom); 512 513 cedrus_write(dev, VE_DEC_H265_DEC_SLICE_HDR_INFO2, reg); 514 515 /* Decoded picture size. */ 516 517 reg = VE_DEC_H265_DEC_PIC_SIZE_WIDTH(ctx->src_fmt.width) | 518 VE_DEC_H265_DEC_PIC_SIZE_HEIGHT(ctx->src_fmt.height); 519 520 cedrus_write(dev, VE_DEC_H265_DEC_PIC_SIZE, reg); 521 522 /* Scaling list. */ 523 524 reg = VE_DEC_H265_SCALING_LIST_CTRL0_DEFAULT; 525 cedrus_write(dev, VE_DEC_H265_SCALING_LIST_CTRL0, reg); 526 527 /* Neightbor information address. */ 528 reg = VE_DEC_H265_NEIGHBOR_INFO_ADDR_BASE(ctx->codec.h265.neighbor_info_buf_addr); 529 cedrus_write(dev, VE_DEC_H265_NEIGHBOR_INFO_ADDR, reg); 530 531 /* Write decoded picture buffer in pic list. */ 533 decode_params->num_active_dpb_entries); 534 535 /* Output frame. */ 536 537 output_pic_list_index = V4L2_HEVC_DPB_ENTRIES_NUM_MAX; 538 pic_order_cnt[0] = slice_params->slice_pic_order_cnt; 539 pic_order_cnt[1] = slice_params->slice_pic_order_cnt; 540 541 cedrus_h265_frame_info_write_single(ctx, output_pic_list_index, 542 slice_params->pic_struct != 0, 543 pic_order_cnt, 544 run->dst->vb2_buf.index); 545 546 cedrus_write(dev, VE_DEC_H265_OUTPUT_FRAME_IDX, output_pic_list_index); 547 548 /* Reference picture list 0 (for P/B frames). */ 549 if (slice_params->slice_type != V4L2_HEVC_SLICE_TYPE_I) { 550 cedrus_h265_ref_pic_list_write(dev, slice_params->dpb, 551 slice_params->ref_idx_l0, 552 slice_params->num_ref_idx_l0_active_minus1 + 1, 553 VE_DEC_H265_SRAM_OFFSET_REF_PIC_LIST0); 554 555 if ((pps->flags & V4L2_HEVC_PPS_FLAG_WEIGHTED_PRED) || 556 (pps->flags & V4L2_HEVC_PPS_FLAG_WEIGHTED_BIPRED)) 557 cedrus_h265_pred_weight_write(dev, 558 pred_weight_table->delta_luma_weight_l0, 559 pred_weight_table->luma_offset_l0, 560 pred_weight_table->delta_chroma_weight_l0, 561 pred_weight_table->chroma_offset_l0, 562 slice_params->num_ref_idx_l0_active_minus1 + 1, 563 VE_DEC_H265_SRAM_OFFSET_PRED_WEIGHT_LUMA_L0, 564 VE_DEC_H265_SRAM_OFFSET_PRED_WEIGHT_CHROMA_L0); 565 } 566 567 /* Reference picture list 1 (for B frames). */ 568 if (slice_params->slice_type == V4L2_HEVC_SLICE_TYPE_B) { 569 cedrus_h265_ref_pic_list_write(dev, slice_params->dpb, 570 slice_params->ref_idx_l1, 571 slice_params->num_ref_idx_l1_active_minus1 + 1, 572 VE_DEC_H265_SRAM_OFFSET_REF_PIC_LIST1); 573 574 if (pps->flags & V4L2_HEVC_PPS_FLAG_WEIGHTED_BIPRED) 575 cedrus_h265_pred_weight_write(dev, 576 pred_weight_table->delta_luma_weight_l1, 577 pred_weight_table->luma_offset_l1, 578 pred_weight_table->delta_chroma_weight_l1, 579 pred_weight_table->chroma_offset_l1, 580 slice_params->num_ref_idx_l1_active_minus1 + 1, 581 VE_DEC_H265_SRAM_OFFSET_PRED_WEIGHT_LUMA_L1, 582 VE_DEC_H265_SRAM_OFFSET_PRED_WEIGHT_CHROMA_L1); 583 } 584 585 /* Enable appropriate interruptions. */ 586 cedrus_write(dev, VE_DEC_H265_CTRL, VE_DEC_H265_CTRL_IRQ_MASK); 587 } 588 --- 0-DAY CI Kernel Test Service, Intel Corporation https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org