tree: https://github.com/omap-audio/linux-audio peter/linux-next-wip head: 4267b3ab8fe441bf25983bf8288fd3025f67702f commit: d776d15bf481edbaf4c507e24260dfbf680d4e19 [1/62] ASoC: ti: davinci-mcasp: Fix DIT mode support config: arm-randconfig-r035-20210611 (attached as .config) compiler: clang version 13.0.0 (https://github.com/llvm/llvm-project d2012d965d60c3258b3a69d024491698f8aec386) reproduce (this is a W=1 build): wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross chmod +x ~/bin/make.cross # install arm cross compiling tool for clang build # apt-get install binutils-arm-linux-gnueabi # https://github.com/omap-audio/linux-audio/commit/d776d15bf481edbaf4c507e2... git remote add omap-audio https://github.com/omap-audio/linux-audio git fetch --no-tags omap-audio peter/linux-next-wip git checkout d776d15bf481edbaf4c507e24260dfbf680d4e19 # save the attached .config to linux build tree COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross ARCH=arm If you fix the issue, kindly add following tag as appropriate Reported-by: kernel test robot <lkp(a)intel.com&gt; All warnings (new ones prefixed by >>): u8 slots = mcasp->op_mode == DAVINCI_MCASP_DIT_MODE ? 384 : mcasp->tdm_slots; ~~~~~ ^~~ 1 warning generated. vim +863 sound/soc/ti/davinci-mcasp.c 855 856 static int mcasp_common_hw_param(struct davinci_mcasp *mcasp, int stream, 857 int period_words, int channels) 858 { 859 struct snd_dmaengine_dai_dma_data *dma_data = &mcasp->dma_data[stream]; 860 int i; 861 u8 tx_ser = 0; 862 u8 rx_ser = 0; 864 u8 max_active_serializers = (channels + slots - 1) / slots; 865 u8 max_rx_serializers, max_tx_serializers; 866 int active_serializers, numevt; 867 u32 reg; 868 /* Default configuration */ 869 if (mcasp->version < MCASP_VERSION_3) 870 mcasp_set_bits(mcasp, DAVINCI_MCASP_PWREMUMGT_REG, MCASP_SOFT); 871 872 if (stream == SNDRV_PCM_STREAM_PLAYBACK) { 873 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF); 874 mcasp_clr_bits(mcasp, DAVINCI_MCASP_XEVTCTL_REG, TXDATADMADIS); 875 max_tx_serializers = max_active_serializers; 876 max_rx_serializers = 877 mcasp->active_serializers[SNDRV_PCM_STREAM_CAPTURE]; 878 } else { 879 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF); 880 mcasp_clr_bits(mcasp, DAVINCI_MCASP_REVTCTL_REG, RXDATADMADIS); 881 max_tx_serializers = 882 mcasp->active_serializers[SNDRV_PCM_STREAM_PLAYBACK]; 883 max_rx_serializers = max_active_serializers; 884 } 885 886 for (i = 0; i < mcasp->num_serializer; i++) { 887 mcasp_set_bits(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i), 888 mcasp->serial_dir[i]); 889 if (mcasp->serial_dir[i] == TX_MODE && 890 tx_ser < max_tx_serializers) { 891 mcasp_mod_bits(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i), 892 mcasp->dismod, DISMOD_MASK); 893 set_bit(PIN_BIT_AXR(i), &mcasp->pdir); 894 tx_ser++; 895 } else if (mcasp->serial_dir[i] == RX_MODE && 896 rx_ser < max_rx_serializers) { 897 clear_bit(PIN_BIT_AXR(i), &mcasp->pdir); 898 rx_ser++; 899 } else { 900 /* Inactive or unused pin, set it to inactive */ 901 mcasp_mod_bits(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i), 902 SRMOD_INACTIVE, SRMOD_MASK); 903 /* If unused, set DISMOD for the pin */ 904 if (mcasp->serial_dir[i] != INACTIVE_MODE) 905 mcasp_mod_bits(mcasp, 906 DAVINCI_MCASP_XRSRCTL_REG(i), 907 mcasp->dismod, DISMOD_MASK); 908 clear_bit(PIN_BIT_AXR(i), &mcasp->pdir); 909 } 910 } 911 912 if (stream == SNDRV_PCM_STREAM_PLAYBACK) { 913 active_serializers = tx_ser; 914 numevt = mcasp->txnumevt; 915 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET; 916 } else { 917 active_serializers = rx_ser; 918 numevt = mcasp->rxnumevt; 919 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET; 920 } 921 922 if (mcasp->op_mode == DAVINCI_MCASP_IIS_MODE) { 923 if (active_serializers < max_active_serializers) { 924 dev_warn(mcasp->dev, "stream has more channels (%d) than are " 925 "enabled in mcasp (%d)\n", channels, 926 active_serializers * slots); 927 return -EINVAL; 928 } 929 } 930 931 /* AFIFO is not in use */ 932 if (!numevt) { 933 /* Configure the burst size for platform drivers */ 934 if (active_serializers > 1) { 935 /* 936 * If more than one serializers are in use we have one 937 * DMA request to provide data for all serializers. 938 * For example if three serializers are enabled the DMA 939 * need to transfer three words per DMA request. 940 */ 941 dma_data->maxburst = active_serializers; 942 } else { 943 dma_data->maxburst = 0; 944 } 945 946 goto out; 947 } 948 949 if (period_words % active_serializers) { 950 dev_err(mcasp->dev, "Invalid combination of period words and " 951 "active serializers: %d, %d\n", period_words, 952 active_serializers); 953 return -EINVAL; 954 } 955 956 /* 957 * Calculate the optimal AFIFO depth for platform side: 958 * The number of words for numevt need to be in steps of active 959 * serializers. 960 */ 961 numevt = (numevt / active_serializers) * active_serializers; 962 963 while (period_words % numevt && numevt > 0) 964 numevt -= active_serializers; 965 if (numevt <= 0) 966 numevt = active_serializers; 967 968 mcasp_mod_bits(mcasp, reg, active_serializers, NUMDMA_MASK); 969 mcasp_mod_bits(mcasp, reg, NUMEVT(numevt), NUMEVT_MASK); 970 971 /* Configure the burst size for platform drivers */ 972 if (numevt == 1) 973 numevt = 0; 974 dma_data->maxburst = numevt; 975 976 out: 977 mcasp->active_serializers[stream] = active_serializers; 978 979 return 0; 980 } 981 --- 0-DAY CI Kernel Test Service, Intel Corporation https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org