tree: https://github.com/miquelraynal/linux-0day.git perso/nand-next/flags head: c5212e24213cba25bcc57e3bbe0781f3e9d83611 commit: 6d5ee825680e1159806682203480f85853f3d03f [98/102] subpage flags merged, could be better config: h8300-randconfig-r003-20200512 (attached as .config) compiler: h8300-linux-gcc (GCC) 9.3.0 reproduce: wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross chmod +x ~/bin/make.cross git checkout 6d5ee825680e1159806682203480f85853f3d03f # save the attached .config to linux build tree COMPILER_INSTALL_PATH=$HOME/0day GCC_VERSION=9.3.0 make.cross ARCH=h8300 If you fix the issue, kindly add following tag as appropriate Reported-by: kbuild test robot <lkp(a)intel.com&gt; All errors (new ones prefixed by >>): drivers/mtd/nand/raw/davinci_nand.c: In function 'nand_davinci_probe': 761 | info->chip.controller.flags = pdata->controller_flags; | ^ | -> vim +761 drivers/mtd/nand/raw/davinci_nand.c 687 688 static int nand_davinci_probe(struct platform_device *pdev) 689 { 690 struct davinci_nand_pdata *pdata; 691 struct davinci_nand_info *info; 692 struct resource *res1; 693 struct resource *res2; 694 void __iomem *vaddr; 695 void __iomem *base; 696 int ret; 697 uint32_t val; 698 struct mtd_info *mtd; 699 700 pdata = nand_davinci_get_pdata(pdev); 701 if (IS_ERR(pdata)) 702 return PTR_ERR(pdata); 703 704 /* insist on board-specific configuration */ 705 if (!pdata) 706 return -ENODEV; 707 708 /* which external chipselect will we be managing? */ 709 if (pdata->core_chipsel < 0 || pdata->core_chipsel > 3) 710 return -ENODEV; 711 712 info = devm_kzalloc(&pdev->dev, sizeof(*info), GFP_KERNEL); 713 if (!info) 714 return -ENOMEM; 715 716 platform_set_drvdata(pdev, info); 717 718 res1 = platform_get_resource(pdev, IORESOURCE_MEM, 0); 719 res2 = platform_get_resource(pdev, IORESOURCE_MEM, 1); 720 if (!res1 || !res2) { 721 dev_err(&pdev->dev, "resource missing\n"); 722 return -EINVAL; 723 } 724 725 vaddr = devm_ioremap_resource(&pdev->dev, res1); 726 if (IS_ERR(vaddr)) 727 return PTR_ERR(vaddr); 728 729 /* 730 * This registers range is used to setup NAND settings. In case with 731 * TI AEMIF driver, the same memory address range is requested already 732 * by AEMIF, so we cannot request it twice, just ioremap. 733 * The AEMIF and NAND drivers not use the same registers in this range. 734 */ 735 base = devm_ioremap(&pdev->dev, res2->start, resource_size(res2)); 736 if (!base) { 737 dev_err(&pdev->dev, "ioremap failed for resource %pR\n", res2); 738 return -EADDRNOTAVAIL; 739 } 740 741 nand_controller_init(&info->controller); 742 info->controller.ops = &davinci_nand_controller_ops; 743 744 info->pdev = pdev; 745 info->base = base; 746 info->vaddr = vaddr; 747 748 mtd = nand_to_mtd(&info->chip); 749 mtd->dev.parent = &pdev->dev; 750 nand_set_flash_node(&info->chip, pdev->dev.of_node); 751 752 info->chip.legacy.IO_ADDR_R = vaddr; 753 info->chip.legacy.IO_ADDR_W = vaddr; 754 info->chip.legacy.chip_delay = 0; 755 info->chip.legacy.select_chip = nand_davinci_select_chip; 756 757 /* options such as NAND_BBT_USE_FLASH */ 758 info->chip.bbt_options = pdata->bbt_options; 759 /* options such as 16-bit widths */ 760 info->chip.options = pdata->options; 762 info->chip.bbt_td = pdata->bbt_td; 763 info->chip.bbt_md = pdata->bbt_md; 764 info->timing = pdata->timing; 765 766 info->current_cs = info->vaddr; 767 info->core_chipsel = pdata->core_chipsel; 768 info->mask_chipsel = pdata->mask_chipsel; 769 770 /* use nandboot-capable ALE/CLE masks by default */ 771 info->mask_ale = pdata->mask_ale ? : MASK_ALE; 772 info->mask_cle = pdata->mask_cle ? : MASK_CLE; 773 774 /* Set address of hardware control function */ 775 info->chip.legacy.cmd_ctrl = nand_davinci_hwcontrol; 776 info->chip.legacy.dev_ready = nand_davinci_dev_ready; 777 778 /* Speed up buffer I/O */ 779 info->chip.legacy.read_buf = nand_davinci_read_buf; 780 info->chip.legacy.write_buf = nand_davinci_write_buf; 781 782 /* Use board-specific ECC config */ 783 info->chip.ecc.mode = pdata->ecc_mode; 784 785 spin_lock_irq(&davinci_nand_lock); 786 787 /* put CSxNAND into NAND mode */ 788 val = davinci_nand_readl(info, NANDFCR_OFFSET); 789 val |= BIT(info->core_chipsel); 790 davinci_nand_writel(info, NANDFCR_OFFSET, val); 791 792 spin_unlock_irq(&davinci_nand_lock); 793 794 /* Scan to find existence of the device(s) */ 795 ret = nand_scan(&info->chip, pdata->mask_chipsel ? 2 : 1); 796 if (ret < 0) { 797 dev_dbg(&pdev->dev, "no NAND chip(s) found\n"); 798 return ret; 799 } 800 801 if (pdata->parts) 802 ret = mtd_device_register(mtd, pdata->parts, pdata->nr_parts); 803 else 804 ret = mtd_device_register(mtd, NULL, 0); 805 if (ret < 0) 806 goto err_cleanup_nand; 807 808 val = davinci_nand_readl(info, NRCSR_OFFSET); 809 dev_info(&pdev->dev, "controller rev. %d.%d\n", 810 (val >> 8) & 0xff, val & 0xff); 811 812 return 0; 813 814 err_cleanup_nand: 815 nand_cleanup(&info->chip); 816 817 return ret; 818 } 819 --- 0-DAY CI Kernel Test Service, Intel Corporation https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org