tree: https://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git pci-probe-cleanups head: 67354513c9a00c91765cfc10c5b1d3db6d993c26 commit: 304c80c4161342d03eab2180bed555b9d3cc6852 [27/35] PCI: Move setting pci_host_bridge.busnr out of host drivers config: arm64-allyesconfig (attached as .config) compiler: aarch64-linux-gcc (GCC) 9.3.0 reproduce (this is a W=1 build): wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross chmod +x ~/bin/make.cross git checkout 304c80c4161342d03eab2180bed555b9d3cc6852 # save the attached .config to linux build tree COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-9.3.0 make.cross ARCH=arm64 If you fix the issue, kindly add following tag as appropriate Reported-by: kernel test robot <lkp(a)intel.com&gt; All errors (new ones prefixed by >>): drivers/pci/controller/dwc/pcie-al.c: In function 'al_pcie_config_prepare': 318 | target_bus_cfg->reg_val = pp->busn->start & target_bus_cfg->reg_mask; | ^~ drivers/pci/controller/dwc/pcie-al.c:323:20: error: 'struct pcie_port' has no member named 'busn' 323 | secondary_bus = pp->busn->start + 1; | ^~ drivers/pci/controller/dwc/pcie-al.c:324:22: error: 'struct pcie_port' has no member named 'busn' 324 | subordinate_bus = pp->busn->end; | ^~ vim +318 drivers/pci/controller/dwc/pcie-al.c a8daea94754989 Jonathan Chocron 2019-09-12 294 a8daea94754989 Jonathan Chocron 2019-09-12 295 static void al_pcie_config_prepare(struct al_pcie *pcie) a8daea94754989 Jonathan Chocron 2019-09-12 296 { a8daea94754989 Jonathan Chocron 2019-09-12 297 struct al_pcie_target_bus_cfg *target_bus_cfg; a8daea94754989 Jonathan Chocron 2019-09-12 298 struct pcie_port *pp = &pcie->pci->pp; a8daea94754989 Jonathan Chocron 2019-09-12 299 unsigned int ecam_bus_mask; a8daea94754989 Jonathan Chocron 2019-09-12 300 u32 cfg_control_offset; a8daea94754989 Jonathan Chocron 2019-09-12 301 u8 subordinate_bus; a8daea94754989 Jonathan Chocron 2019-09-12 302 u8 secondary_bus; a8daea94754989 Jonathan Chocron 2019-09-12 303 u32 cfg_control; a8daea94754989 Jonathan Chocron 2019-09-12 304 u32 reg; a8daea94754989 Jonathan Chocron 2019-09-12 305 a8daea94754989 Jonathan Chocron 2019-09-12 306 target_bus_cfg = &pcie->target_bus_cfg; a8daea94754989 Jonathan Chocron 2019-09-12 307 a8daea94754989 Jonathan Chocron 2019-09-12 308 ecam_bus_mask = (pcie->ecam_size >> 20) - 1; a8daea94754989 Jonathan Chocron 2019-09-12 309 if (ecam_bus_mask > 255) { a8daea94754989 Jonathan Chocron 2019-09-12 310 dev_warn(pcie->dev, "ECAM window size is larger than 256MB. Cutting off at 256\n"); a8daea94754989 Jonathan Chocron 2019-09-12 311 ecam_bus_mask = 255; a8daea94754989 Jonathan Chocron 2019-09-12 312 } a8daea94754989 Jonathan Chocron 2019-09-12 313 a8daea94754989 Jonathan Chocron 2019-09-12 314 /* This portion is taken from the transaction address */ a8daea94754989 Jonathan Chocron 2019-09-12 315 target_bus_cfg->ecam_mask = ecam_bus_mask; a8daea94754989 Jonathan Chocron 2019-09-12 316 /* This portion is taken from the cfg_target_bus reg */ a8daea94754989 Jonathan Chocron 2019-09-12 317 target_bus_cfg->reg_mask = ~target_bus_cfg->ecam_mask; a8daea94754989 Jonathan Chocron 2019-09-12 @318 target_bus_cfg->reg_val = pp->busn->start & target_bus_cfg->reg_mask; a8daea94754989 Jonathan Chocron 2019-09-12 319 a8daea94754989 Jonathan Chocron 2019-09-12 320 al_pcie_target_bus_set(pcie, target_bus_cfg->reg_val, a8daea94754989 Jonathan Chocron 2019-09-12 321 target_bus_cfg->reg_mask); a8daea94754989 Jonathan Chocron 2019-09-12 322 a8daea94754989 Jonathan Chocron 2019-09-12 323 secondary_bus = pp->busn->start + 1; a8daea94754989 Jonathan Chocron 2019-09-12 324 subordinate_bus = pp->busn->end; a8daea94754989 Jonathan Chocron 2019-09-12 325 a8daea94754989 Jonathan Chocron 2019-09-12 326 /* Set the valid values of secondary and subordinate buses */ a8daea94754989 Jonathan Chocron 2019-09-12 327 cfg_control_offset = AXI_BASE_OFFSET + pcie->reg_offsets.ob_ctrl + a8daea94754989 Jonathan Chocron 2019-09-12 328 CFG_CONTROL; a8daea94754989 Jonathan Chocron 2019-09-12 329 a8daea94754989 Jonathan Chocron 2019-09-12 330 cfg_control = al_pcie_controller_readl(pcie, cfg_control_offset); a8daea94754989 Jonathan Chocron 2019-09-12 331 a8daea94754989 Jonathan Chocron 2019-09-12 332 reg = cfg_control & a8daea94754989 Jonathan Chocron 2019-09-12 333 ~(CFG_CONTROL_SEC_BUS_MASK | CFG_CONTROL_SUBBUS_MASK); a8daea94754989 Jonathan Chocron 2019-09-12 334 a8daea94754989 Jonathan Chocron 2019-09-12 335 reg |= FIELD_PREP(CFG_CONTROL_SUBBUS_MASK, subordinate_bus) | a8daea94754989 Jonathan Chocron 2019-09-12 336 FIELD_PREP(CFG_CONTROL_SEC_BUS_MASK, secondary_bus); a8daea94754989 Jonathan Chocron 2019-09-12 337 a8daea94754989 Jonathan Chocron 2019-09-12 338 al_pcie_controller_writel(pcie, cfg_control_offset, reg); a8daea94754989 Jonathan Chocron 2019-09-12 339 } a8daea94754989 Jonathan Chocron 2019-09-12 340 :::::: The code at line 318 was first introduced by commit :::::: a8daea94754989f6c48dafda840482cbc9f882f9 PCI: dwc: al: Add Amazon Annapurna Labs PCIe controller driver :::::: TO: Jonathan Chocron <jonnyc(a)amazon.com&gt; :::::: CC: Lorenzo Pieralisi <lorenzo.pieralisi(a)arm.com&gt; --- 0-DAY CI Kernel Test Service, Intel Corporation https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org