tree:
https://git.kernel.org/pub/scm/linux/kernel/git/sashal/linux-stable.git
pending-5.13
head: 9e20d32ceee869b30775be931beb33f561a4f955
commit: 6fbba0e81319c3e92bc038421cb1750160cb74bd [106/176] drm/amd/display: Cover
edge-case when changing DISPCLK WDIVIDER
config: i386-randconfig-a003-20210715 (attached as .config)
compiler: gcc-10 (Ubuntu 10.3.0-1ubuntu1~20.04) 10.3.0
reproduce (this is a W=1 build):
#
https://git.kernel.org/pub/scm/linux/kernel/git/sashal/linux-stable.git/c...
git remote add sashal-linux-stable
https://git.kernel.org/pub/scm/linux/kernel/git/sashal/linux-stable.git
git fetch --no-tags sashal-linux-stable pending-5.13
git checkout 6fbba0e81319c3e92bc038421cb1750160cb74bd
# save the attached .config to linux build tree
mkdir build_dir
make W=1 O=build_dir ARCH=i386 SHELL=/bin/bash
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp(a)intel.com>
All errors (new ones prefixed by >>):
drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c: In function
'dcn20_update_clocks_update_dentist':
>
drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c:154:26: error:
'const struct stream_encoder_funcs' has no member named
'get_fifo_cal_average_level'
154 | if
(!stream_enc->funcs->get_fifo_cal_average_level)
| ^~
drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c:156:34: error:
'const struct stream_encoder_funcs' has no member named
'get_fifo_cal_average_level'
156 | fifo_level = stream_enc->funcs->get_fifo_cal_average_level(
| ^~
>
drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c:159:15: error:
'const struct dccg_funcs' has no member named 'set_fifo_errdet_ovr_en'
159 | dccg->funcs->set_fifo_errdet_ovr_en(
| ^~
>
drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c:163:16: error:
'const struct dccg_funcs' has no member named 'otg_drop_pixel'
163 | dccg->funcs->otg_drop_pixel(
| ^~
drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c:166:15: error:
'const struct dccg_funcs' has no member named 'set_fifo_errdet_ovr_en'
166 | dccg->funcs->set_fifo_errdet_ovr_en(
| ^~
drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c:185:26: error:
'const struct stream_encoder_funcs' has no member named
'get_fifo_cal_average_level'
185 | if (!stream_enc->funcs->get_fifo_cal_average_level)
| ^~
drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c:187:34: error:
'const struct stream_encoder_funcs' has no member named
'get_fifo_cal_average_level'
187 | fifo_level = stream_enc->funcs->get_fifo_cal_average_level(
| ^~
drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c:190:15: error:
'const struct dccg_funcs' has no member named 'set_fifo_errdet_ovr_en'
190 | dccg->funcs->set_fifo_errdet_ovr_en(dccg, true);
| ^~
>
drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c:192:16: error:
'const struct dccg_funcs' has no member named 'otg_add_pixel'
192 | dccg->funcs->otg_add_pixel(dccg,
| ^~
drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c:194:15: error:
'const struct dccg_funcs' has no member named 'set_fifo_errdet_ovr_en'
194 | dccg->funcs->set_fifo_errdet_ovr_en(dccg, false);
| ^~
drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c: At top level:
drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c:400:6: warning:
no previous prototype for 'dcn2_enable_pme_wa' [-Wmissing-prototypes]
400 | void dcn2_enable_pme_wa(struct clk_mgr *clk_mgr_base)
| ^~~~~~~~~~~~~~~~~~
vim +154 drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c
125
126 void dcn20_update_clocks_update_dentist(struct clk_mgr_internal *clk_mgr, struct
dc_state *context)
127 {
128 int dpp_divider = DENTIST_DIVIDER_RANGE_SCALE_FACTOR
129 * clk_mgr->base.dentist_vco_freq_khz / clk_mgr->base.clks.dppclk_khz;
130 int disp_divider = DENTIST_DIVIDER_RANGE_SCALE_FACTOR
131 * clk_mgr->base.dentist_vco_freq_khz / clk_mgr->base.clks.dispclk_khz;
132
133 uint32_t dppclk_wdivider = dentist_get_did_from_divider(dpp_divider);
134 uint32_t dispclk_wdivider = dentist_get_did_from_divider(disp_divider);
135 uint32_t current_dispclk_wdivider;
136 uint32_t i;
137
138 REG_GET(DENTIST_DISPCLK_CNTL,
139 DENTIST_DISPCLK_WDIVIDER, ¤t_dispclk_wdivider);
140
141 /* When changing divider to or from 127, some extra programming is required to
prevent corruption */
142 if (current_dispclk_wdivider == 127 && dispclk_wdivider != 127) {
143 for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++)
{
144 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
145 uint32_t fifo_level;
146 struct dccg *dccg = clk_mgr->base.ctx->dc->res_pool->dccg;
147 struct stream_encoder *stream_enc = pipe_ctx->stream_res.stream_enc;
148 int32_t N;
149 int32_t j;
150
151 if (!pipe_ctx->stream)
152 continue;
153 /* Virtual encoders don't have this function */
154 if (!stream_enc->funcs->get_fifo_cal_average_level)
155 continue;
156 fifo_level = stream_enc->funcs->get_fifo_cal_average_level(
157 stream_enc);
158 N = fifo_level / 4;
159 dccg->funcs->set_fifo_errdet_ovr_en(
160 dccg,
161 true);
162 for (j = 0; j < N - 4; j++)
163 dccg->funcs->otg_drop_pixel(
164 dccg,
165 pipe_ctx->stream_res.tg->inst);
166 dccg->funcs->set_fifo_errdet_ovr_en(
167 dccg,
168 false);
169 }
170 } else if (dispclk_wdivider == 127 && current_dispclk_wdivider != 127) {
171 REG_UPDATE(DENTIST_DISPCLK_CNTL,
172 DENTIST_DISPCLK_WDIVIDER, 126);
173 REG_WAIT(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_CHG_DONE, 1, 50, 100);
174 for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++)
{
175 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
176 struct dccg *dccg = clk_mgr->base.ctx->dc->res_pool->dccg;
177 struct stream_encoder *stream_enc = pipe_ctx->stream_res.stream_enc;
178 uint32_t fifo_level;
179 int32_t N;
180 int32_t j;
181
182 if (!pipe_ctx->stream)
183 continue;
184 /* Virtual encoders don't have this function */
185 if (!stream_enc->funcs->get_fifo_cal_average_level)
186 continue;
187 fifo_level = stream_enc->funcs->get_fifo_cal_average_level(
188 stream_enc);
189 N = fifo_level / 4;
190 dccg->funcs->set_fifo_errdet_ovr_en(dccg, true);
191 for (j = 0; j < 12 - N; j++)
192 dccg->funcs->otg_add_pixel(dccg,
193 pipe_ctx->stream_res.tg->inst);
194 dccg->funcs->set_fifo_errdet_ovr_en(dccg, false);
195 }
196 }
197
198 REG_UPDATE(DENTIST_DISPCLK_CNTL,
199 DENTIST_DISPCLK_WDIVIDER, dispclk_wdivider);
200 // REG_WAIT(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_CHG_DONE, 1, 5, 100);
201 REG_UPDATE(DENTIST_DISPCLK_CNTL,
202 DENTIST_DPPCLK_WDIVIDER, dppclk_wdivider);
203 REG_WAIT(DENTIST_DISPCLK_CNTL, DENTIST_DPPCLK_CHG_DONE, 1, 5, 100);
204 }
205
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org