tree: https://git.kernel.org/pub/scm/linux/kernel/git/kvalo/ath.git ath11k-qca6390-bringup head: 682bd79bb8fe637b426947462daa7bdf155b198a commit: 682bd79bb8fe637b426947462daa7bdf155b198a [67/67] ath11k: reset MHI during power down and power up config: i386-allyesconfig (attached as .config) compiler: gcc-9 (Debian 9.3.0-13) 9.3.0 reproduce (this is a W=1 build): git checkout 682bd79bb8fe637b426947462daa7bdf155b198a # save the attached .config to linux build tree make W=1 ARCH=i386 If you fix the issue, kindly add following tag as appropriate Reported-by: kernel test robot <lkp(a)intel.com&gt; All warnings (new ones prefixed by >>, old ones prefixed by <<): 362 | void ath11k_pci_soc_global_reset(struct ath11k_base *ab) | ^~~~~~~~~~~~~~~~~~~~~~~~~~~ 389 | void ath11k_pci_clear_dbg_registers(struct ath11k_base *ab) | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 419 | void ath11k_pci_force_wake(struct ath11k_base *ab) | ^~~~~~~~~~~~~~~~~~~~~ 425 | void ath11k_pci_force_wake_release(struct ath11k_base *ab) | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 431 | void ath11k_pci_sw_reset(struct ath11k_base *ab) | ^~~~~~~~~~~~~~~~~~~ drivers/net/wireless/ath/ath11k/pci.c: In function 'ath11k_pci_start': 1078 | struct ath11k_pci *ar_pci; | ^~~~~~ vim +/ath11k_pci_soc_global_reset +362 drivers/net/wireless/ath/ath11k/pci.c 361 363 { 364 u32 val; 365 u32 delay; 366 367 val = ath11k_pci_read32(ab, PCIE_SOC_GLOBAL_RESET); 368 369 val |= PCIE_SOC_GLOBAL_RESET_V; 370 371 ath11k_pci_write32(ab, PCIE_SOC_GLOBAL_RESET, val); 372 373 /* TODO: exact time to sleep is uncertain */ 374 delay = 10; 375 mdelay(delay); 376 377 /* Need to toggle V bit back otherwise stuck in reset status */ 378 val &= ~PCIE_SOC_GLOBAL_RESET_V; 379 380 ath11k_pci_write32(ab, PCIE_SOC_GLOBAL_RESET, val); 381 382 mdelay(delay); 383 384 val = ath11k_pci_read32(ab, PCIE_SOC_GLOBAL_RESET); 385 if (val == 0xffffffff) 386 ath11k_err(ab, "%s link down error\n", __func__); 387 } 388 390 { 391 u32 val; 392 393 /* read cookie */ 394 val = ath11k_pci_read32(ab, PCIE_Q6_COOKIE_ADDR); 395 ath11k_dbg(ab, ATH11K_DBG_PCI, "cookie:0x%x\n", val); 396 397 val = ath11k_pci_read32(ab, WLAON_WARM_SW_ENTRY); 398 ath11k_dbg(ab, ATH11K_DBG_PCI, "WLAON_WARM_SW_ENTRY 0x%x\n", val); 399 400 /* TODO: exact time to sleep is uncertain */ 401 mdelay(10); 402 403 /* write 0 to WLAON_WARM_SW_ENTRY to prevent Q6 from 404 * continuing warm path and entering dead loop. 405 */ 406 ath11k_pci_write32(ab, WLAON_WARM_SW_ENTRY, 0); 407 mdelay(10); 408 409 val = ath11k_pci_read32(ab, WLAON_WARM_SW_ENTRY); 410 ath11k_dbg(ab, ATH11K_DBG_PCI, "WLAON_WARM_SW_ENTRY 0x%x\n", val); 411 412 /* A read clear register. clear the register to prevent 413 * Q6 from entering wrong code path. 414 */ 415 val = ath11k_pci_read32(ab, WLAON_SOC_RESET_CAUSE_REG); 416 ath11k_dbg(ab, ATH11K_DBG_PCI, "soc reset cause:%d\n", val); 417 } 418 420 { 421 ath11k_pci_write32(ab, PCIE_SOC_WAKE_PCIE_LOCAL_REG, 1); 422 mdelay(5); 423 } 424 426 { 427 ath11k_pci_write32(ab, PCIE_SOC_WAKE_PCIE_LOCAL_REG, 0); 428 mdelay(5); 429 } 430 432 { 433 ath11k_pci_soc_global_reset(ab); 434 ath11k_mhi_clear_vector(ab); 435 ath11k_pci_soc_global_reset(ab); 436 ath11k_mhi_set_mhictrl_reset(ab); 437 ath11k_pci_clear_dbg_registers(ab); 438 } 439 --- 0-DAY CI Kernel Test Service, Intel Corporation https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org