11:43 p.m.
Hi "Ramuthevar,Vadivel,
Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on robh/for-next]
[also build test WARNING on arm-soc/for-next linus/master linux/master v5.7-rc5
next-20200514]
[cannot apply to mtd/master]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system. BTW, we also suggest to use '--base' option to specify the
base tree in git format-patch, please see https://stackoverflow.com/a/37406982]
url:
https://github.com/0day-ci/linux/commits/Ramuthevar-Vadivel-MuruganX/mtd-...
base: https://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git for-next
reproduce:
# apt-get install sparse
# sparse version: v0.6.1-193-gb8fad4bc-dirty
make ARCH=x86_64 allmodconfig
make C=1 CF='-fdiagnostic-prefix -D__CHECK_ENDIAN__'
If you fix the issue, kindly add following tag as appropriate
Reported-by: kbuild test robot <lkp(a)intel.com>
sparse warnings: (new ones prefixed by >>)
> drivers/mtd/nand/raw/intel-nand-controller.c:441:24: sparse:
sparse: incorrect type in argument 1 (different base types) @@ expected unsigned int
val @@ got restricted __be32 [assignedunsigned int val @@
> drivers/mtd/nand/raw/intel-nand-controller.c:441:24: sparse: expected unsigned int
val
> drivers/mtd/nand/raw/intel-nand-controller.c:441:24: sparse: got restricted __be32
[assigned] [usertype] reg
drivers/mtd/nand/raw/intel-nand-controller.c:444:24:
sparse: sparse: incorrect type in argument 1 (different base types) @@ expected
unsigned int val @@ got restricted __be32 [assignedunsigned int val @@
drivers/mtd/nand/raw/intel-nand-controller.c:444:24: sparse: expected unsigned int
val
drivers/mtd/nand/raw/intel-nand-controller.c:444:24: sparse: got restricted __be32
[assigned] [usertype] reg
vim +441 drivers/mtd/nand/raw/intel-nand-controller.c
420
421 static int ebu_nand_write_page_hwecc(struct nand_chip *chip, const u8 *buf,
422 int oob_required, int page)
423 {
424 struct mtd_info *mtd = nand_to_mtd(chip);
425 struct ebu_nand_controller *ebu_host = nand_get_controller_data(chip);
426 void __iomem *int_sta = ebu_host->hsnand + HSNAND_INT_STA;
427 int ret, val, x;
428 __be32 reg;
429
430 ebu_nand_trigger(ebu_host, page, NAND_CMD_SEQIN);
431
432 ret = ebu_dma_start(ebu_host, DMA_MEM_TO_DEV, buf, mtd->writesize);
433 if (ret)
434 return ret;
435
436 if (oob_required) {
437 const u8 *pdata;
438
439 pdata = chip->oob_poi;
440 reg = cpu_to_be32(*pdata++);
441 writel(reg, ebu_host->hsnand + HSNAND_CMSG_0);
442
443 reg = cpu_to_be32(*pdata);
444 writel(reg, ebu_host->hsnand + HSNAND_CMSG_1);
445 }
446
447 ret = readl_poll_timeout_atomic(int_sta, val,
448 !(val & HSNAND_INT_STA_WR_C), 10, 1000);
449 if (ret)
450 return -EIO;
451
452 x = readl(ebu_host->hsnand + HSNAND_CTL);
453 x &= ~HSNAND_CTL_GO;
454 writel(x, ebu_host->hsnand + HSNAND_CTL);
455
456 return 0;
457 }
458
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
12:25 a.m.
New subject: [PATCH v7 2/2] mtd: rawnand: Add NAND controller support on Intel LGM SoC
On Fri, May 15, 2020 at 4:48 PM kbuild test robot <lkp(a)intel.com> wrote:
sparse warnings: (new ones prefixed by >>)
>> drivers/mtd/nand/raw/intel-nand-controller.c:441:24: sparse: sparse: incorrect
type in argument 1 (different base types) @@ expected unsigned int val @@ got
restricted __be32 [assignedunsigned int val @@
>> drivers/mtd/nand/raw/intel-nand-controller.c:441:24: sparse: expected
unsigned int val
>> drivers/mtd/nand/raw/intel-nand-controller.c:441:24: sparse: got restricted
__be32 [assigned] [usertype] reg
drivers/mtd/nand/raw/intel-nand-controller.c:444:24: sparse: sparse: incorrect type in
argument 1 (different base types) @@ expected unsigned int val @@ got restricted
__be32 [assignedunsigned int val @@
drivers/mtd/nand/raw/intel-nand-controller.c:444:24: sparse: expected unsigned int
val
drivers/mtd/nand/raw/intel-nand-controller.c:444:24: sparse: got restricted __be32
[assigned] [usertype] reg
440 reg = cpu_to_be32(*pdata++);
> 441 writel(reg, ebu_host->hsnand + HSNAND_CMSG_0);
442
443 reg = cpu_to_be32(*pdata);
444 writel(reg, ebu_host->hsnand + HSNAND_CMSG_1);
On BE:
cpu_to_be32 -> no-op
writel() -> converts reg to LE
On LE:
cpu_to_be32 -> converts to BE
writel() -> no-op (in terms of conversion)
Seems to me that the proper API (if above is intended) should be swab32().
But something tells me that above is broken (or my understanding is wrong).
--
With Best Regards,
Andy Shevchenko
12:27 a.m.
New subject: [PATCH v7 2/2] mtd: rawnand: Add NAND controller support on Intel LGM SoC
On Fri, May 15, 2020 at 5:25 PM Andy Shevchenko
<andy.shevchenko(a)gmail.com> wrote:
On Fri, May 15, 2020 at 4:48 PM kbuild test robot
<lkp(a)intel.com> wrote:
> 440 reg = cpu_to_be32(*pdata++);
> > 441 writel(reg, ebu_host->hsnand + HSNAND_CMSG_0);
> 442
> 443 reg = cpu_to_be32(*pdata);
> 444 writel(reg, ebu_host->hsnand + HSNAND_CMSG_1);
On BE:
cpu_to_be32 -> no-op
writel() -> converts reg to LE
On LE:
cpu_to_be32 -> converts to BE
writel() -> no-op (in terms of conversion)
Seems to me that the proper API (if above is intended) should be swab32().
But something tells me that above is broken (or my understanding is wrong).
And perhaps it should use lo_hi_writeq() or something like that.
--
With Best Regards,
Andy Shevchenko
12:30 a.m.
New subject: [PATCH v7 2/2] mtd: rawnand: Add NAND controller support on Intel LGM SoC
On Fri, May 15, 2020 at 4:25 PM Andy Shevchenko
<andy.shevchenko(a)gmail.com> wrote:
On Fri, May 15, 2020 at 4:48 PM kbuild test robot <lkp(a)intel.com> wrote:
> sparse warnings: (new ones prefixed by >>)
>
> >> drivers/mtd/nand/raw/intel-nand-controller.c:441:24: sparse: sparse:
incorrect type in argument 1 (different base types) @@ expected unsigned int val @@
got restricted __be32 [assignedunsigned int val @@
> >> drivers/mtd/nand/raw/intel-nand-controller.c:441:24: sparse: expected
unsigned int val
> >> drivers/mtd/nand/raw/intel-nand-controller.c:441:24: sparse: got
restricted __be32 [assigned] [usertype] reg
> drivers/mtd/nand/raw/intel-nand-controller.c:444:24: sparse: sparse: incorrect
type in argument 1 (different base types) @@ expected unsigned int val @@ got
restricted __be32 [assignedunsigned int val @@
> drivers/mtd/nand/raw/intel-nand-controller.c:444:24: sparse: expected unsigned
int val
> drivers/mtd/nand/raw/intel-nand-controller.c:444:24: sparse: got restricted
__be32 [assigned] [usertype] reg
>
> 440 reg = cpu_to_be32(*pdata++);
> > 441 writel(reg, ebu_host->hsnand + HSNAND_CMSG_0);
> 442
> 443 reg = cpu_to_be32(*pdata);
> 444 writel(reg, ebu_host->hsnand + HSNAND_CMSG_1);
On BE:
cpu_to_be32 -> no-op
writel() -> converts reg to LE
On LE:
cpu_to_be32 -> converts to BE
writel() -> no-op (in terms of conversion)
Seems to me that the proper API (if above is intended) should be swab32().
But something tells me that above is broken (or my understanding is wrong).
iowrite_be32() is the correct way to store word into a big-endian mmio register,
if that is the intention here.
Arnd
9:39 p.m.
New subject: [PATCH v7 2/2] mtd: rawnand: Add NAND controller support on Intel LGM SoC
Hi Arnd, Andy,
On 15/5/2020 10:30 pm, Arnd Bergmann wrote:
On Fri, May 15, 2020 at 4:25 PM Andy Shevchenko
<andy.shevchenko(a)gmail.com> wrote:
>
> On Fri, May 15, 2020 at 4:48 PM kbuild test robot <lkp(a)intel.com> wrote:
>
>> sparse warnings: (new ones prefixed by >>)
>>
>>>> drivers/mtd/nand/raw/intel-nand-controller.c:441:24: sparse: sparse:
incorrect type in argument 1 (different base types) @@ expected unsigned int val @@
got restricted __be32 [assignedunsigned int val @@
>>>> drivers/mtd/nand/raw/intel-nand-controller.c:441:24: sparse: expected
unsigned int val
>>>> drivers/mtd/nand/raw/intel-nand-controller.c:441:24: sparse: got
restricted __be32 [assigned] [usertype] reg
>> drivers/mtd/nand/raw/intel-nand-controller.c:444:24: sparse: sparse:
incorrect type in argument 1 (different base types) @@ expected unsigned int val @@
got restricted __be32 [assignedunsigned int val @@
>> drivers/mtd/nand/raw/intel-nand-controller.c:444:24: sparse: expected
unsigned int val
>> drivers/mtd/nand/raw/intel-nand-controller.c:444:24: sparse: got
restricted __be32 [assigned] [usertype] reg
>>
>> 440 reg = cpu_to_be32(*pdata++);
>> > 441 writel(reg, ebu_host->hsnand + HSNAND_CMSG_0);
>> 442
>> 443 reg = cpu_to_be32(*pdata);
>> 444 writel(reg, ebu_host->hsnand + HSNAND_CMSG_1);
>
> On BE:
> cpu_to_be32 -> no-op
> writel() -> converts reg to LE
>
> On LE:
> cpu_to_be32 -> converts to BE
> writel() -> no-op (in terms of conversion)
>
> Seems to me that the proper API (if above is intended) should be swab32().
> But something tells me that above is broken (or my understanding is wrong).
iowrite_be32() is the correct way to store word into a big-endian mmio register,
if that is the intention here.
Thank you for suggestions to use iowrite32be(), it
suits exactly.
Regards
Vadivel
>
> Arnd
>
9:43 p.m.
New subject: [PATCH v7 2/2] mtd: rawnand: Add NAND controller support on Intel LGM SoC
On Mon, May 18, 2020 at 2:39 PM Ramuthevar, Vadivel MuruganX
<vadivel.muruganx.ramuthevar(a)linux.intel.com> wrote:
On 15/5/2020 10:30 pm, Arnd Bergmann wrote:
> On Fri, May 15, 2020 at 4:25 PM Andy Shevchenko
> <andy.shevchenko(a)gmail.com> wrote:
>> On Fri, May 15, 2020 at 4:48 PM kbuild test robot <lkp(a)intel.com> wrote:
> iowrite_be32() is the correct way to store word into a
big-endian mmio register,
> if that is the intention here.
Thank you for suggestions to use iowrite32be(), it suits exactly.
Can you before doing this comment what is the real intention here?
And note, if you are going to use iowrite*() / ioread*() in one place,
you will probably need to replace all of the read*() / write*() to
respective io* API.
--
With Best Regards,
Andy Shevchenko
9:57 p.m.
New subject: [PATCH v7 2/2] mtd: rawnand: Add NAND controller support on Intel LGM SoC
On Mon, May 18, 2020 at 1:43 PM Andy Shevchenko
<andy.shevchenko(a)gmail.com> wrote:
On Mon, May 18, 2020 at 2:39 PM Ramuthevar, Vadivel MuruganX
<vadivel.muruganx.ramuthevar(a)linux.intel.com> wrote:
> On 15/5/2020 10:30 pm, Arnd Bergmann wrote:
> > On Fri, May 15, 2020 at 4:25 PM Andy Shevchenko
> > <andy.shevchenko(a)gmail.com> wrote:
> >> On Fri, May 15, 2020 at 4:48 PM kbuild test robot <lkp(a)intel.com>
wrote:
> > iowrite_be32() is the correct way to store word into a big-endian mmio
register,
> > if that is the intention here.
> Thank you for suggestions to use iowrite32be(), it suits exactly.
Can you before doing this comment what is the real intention here?
And note, if you are going to use iowrite*() / ioread*() in one place,
you will probably need to replace all of the read*() / write*() to
respective io* API.
The way that ioread/iowrite are defined, they are required to be a superset
of what readl/writel do and can take __iomem pointers from either
ioremap() or ioport_map()/pci_iomap() style mappings, while readl/writel
are only required to work with ioremap().
There is no technical requirement to stick to one set or the other for
ioremap(), but the overhead of ioread/iowrite is also small enough
that it generally does not hurt.
Arnd
11:20 p.m.
New subject: [PATCH v7 2/2] mtd: rawnand: Add NAND controller support on Intel LGM SoC
On Mon, May 18, 2020 at 2:57 PM Arnd Bergmann <arnd(a)arndb.de> wrote:
On Mon, May 18, 2020 at 1:43 PM Andy Shevchenko
<andy.shevchenko(a)gmail.com> wrote:
> On Mon, May 18, 2020 at 2:39 PM Ramuthevar, Vadivel MuruganX
> <vadivel.muruganx.ramuthevar(a)linux.intel.com> wrote:
> > On 15/5/2020 10:30 pm, Arnd Bergmann wrote:
> > > On Fri, May 15, 2020 at 4:25 PM Andy Shevchenko
> > > <andy.shevchenko(a)gmail.com> wrote:
> > >> On Fri, May 15, 2020 at 4:48 PM kbuild test robot
<lkp(a)intel.com> wrote:
>
> > > iowrite_be32() is the correct way to store word into a big-endian mmio
register,
> > > if that is the intention here.
> > Thank you for suggestions to use iowrite32be(), it suits exactly.
>
> Can you before doing this comment what is the real intention here?
>
> And note, if you are going to use iowrite*() / ioread*() in one place,
> you will probably need to replace all of the read*() / write*() to
> respective io* API.
The way that ioread/iowrite are defined, they are required to be a superset
of what readl/writel do and can take __iomem pointers from either
ioremap() or ioport_map()/pci_iomap() style mappings, while readl/writel
are only required to work with ioremap().
There is no technical requirement to stick to one set or the other for
ioremap(), but the overhead of ioread/iowrite is also small enough
that it generally does not hurt.
Right, my suggestion is solely for consistency. It would be a bit
weird to see readl() along with ioread32() in the same driver (in case
there are no differentiated callbacks specifically for different type
of IP).
--
With Best Regards,
Andy Shevchenko
855
days inactive
858
days old
7 comments
4 participants
participants (4)
-
Andy Shevchenko -
Arnd Bergmann -
kbuild test robot -
Ramuthevar, Vadivel MuruganX