tree: https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git master head: 5fcb9628fd1227a5f11d87171cb1b8b5c414d9d9 commit: c422a628925d9733b0807d803133fb78a0a0f707 [953/2089] drm/amdgpu: rename macro for VCN2.0 2.5 and 3.0 config: i386-allyesconfig (attached as .config) compiler: gcc-9 (Debian 9.3.0-13) 9.3.0 reproduce (this is a W=1 build): git checkout c422a628925d9733b0807d803133fb78a0a0f707 # save the attached .config to linux build tree make W=1 ARCH=i386 If you fix the issue, kindly add following tag as appropriate Reported-by: kernel test robot <lkp(a)intel.com&gt; All warnings (new ones prefixed by >>, old ones prefixed by <<): 446 | void vcn_v2_5_mc_resume_dpg_mode(struct amdgpu_device *adev, int inst_idx, bool indirect) | ^~~~~~~~~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c: In function 'vcn_v2_5_disable_clock_gating': drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c:552:6: warning: variable 'ret' set but not used [-Wunused-but-set-variable] 552 | int ret = 0; | ^~~ drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c: At top level: 660 | void vcn_v2_5_clock_gating_dpg_mode(struct amdgpu_device *adev, | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1303 | int vcn_v2_5_stop_dpg_mode(struct amdgpu_device *adev, int inst_idx) | ^~~~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c: In function 'vcn_v2_5_stop_dpg_mode': drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c:1305:6: warning: variable 'ret_code' set but not used [-Wunused-but-set-variable] 1305 | int ret_code = 0; | ^~~~~~~~ In file included from drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c:26: At top level: drivers/gpu/drm/amd/amdgpu/amdgpu.h:190:18: warning: 'sched_policy' defined but not used [-Wunused-const-variable=] 190 | static const int sched_policy = KFD_SCHED_POLICY_HWS; | ^~~~~~~~~~~~ In file included from drivers/gpu/drm/amd/amdgpu/../display/dc/dc_types.h:33, from drivers/gpu/drm/amd/amdgpu/../display/dc/dm_services_types.h:30, from drivers/gpu/drm/amd/amdgpu/../include/dm_pp_interface.h:26, from drivers/gpu/drm/amd/amdgpu/amdgpu.h:65, from drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c:26: drivers/gpu/drm/amd/amdgpu/../display/include/fixed31_32.h:76:32: warning: 'dc_fixpt_ln2_div_2' defined but not used [-Wunused-const-variable=] 76 | static const struct fixed31_32 dc_fixpt_ln2_div_2 = { 1488522236LL }; | ^~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/include/fixed31_32.h:75:32: warning: 'dc_fixpt_ln2' defined but not used [-Wunused-const-variable=] 75 | static const struct fixed31_32 dc_fixpt_ln2 = { 2977044471LL }; | ^~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/include/fixed31_32.h:74:32: warning: 'dc_fixpt_e' defined but not used [-Wunused-const-variable=] 74 | static const struct fixed31_32 dc_fixpt_e = { 11674931555LL }; | ^~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/include/fixed31_32.h:73:32: warning: 'dc_fixpt_two_pi' defined but not used [-Wunused-const-variable=] 73 | static const struct fixed31_32 dc_fixpt_two_pi = { 26986075409LL }; | ^~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/include/fixed31_32.h:72:32: warning: 'dc_fixpt_pi' defined but not used [-Wunused-const-variable=] 72 | static const struct fixed31_32 dc_fixpt_pi = { 13493037705LL }; | ^~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/include/fixed31_32.h:67:32: warning: 'dc_fixpt_zero' defined but not used [-Wunused-const-variable=] 67 | static const struct fixed31_32 dc_fixpt_zero = { 0 }; | ^~~~~~~~~~~~~ vim +/vcn_v2_5_mc_resume_dpg_mode +446 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c 445 447 { 448 uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4); 449 uint32_t offset; 450 451 /* cache window 0: fw */ 452 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 453 if (!indirect) { 454 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 455 VCN, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 456 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_lo), 0, indirect); 457 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 458 VCN, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 459 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_hi), 0, indirect); 460 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 461 VCN, 0, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); 462 } else { 463 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 464 VCN, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 0, 0, indirect); 465 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 466 VCN, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 0, 0, indirect); 467 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 468 VCN, 0, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); 469 } 470 offset = 0; 471 } else { 472 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 473 VCN, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 474 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect); 475 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 476 VCN, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 477 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect); 478 offset = size; 479 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 480 VCN, 0, mmUVD_VCPU_CACHE_OFFSET0), 481 AMDGPU_UVD_FIRMWARE_OFFSET >> 3, 0, indirect); 482 } 483 484 if (!indirect) 485 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 486 VCN, 0, mmUVD_VCPU_CACHE_SIZE0), size, 0, indirect); 487 else 488 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 489 VCN, 0, mmUVD_VCPU_CACHE_SIZE0), 0, 0, indirect); 490 491 /* cache window 1: stack */ 492 if (!indirect) { 493 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 494 VCN, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 495 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect); 496 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 497 VCN, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 498 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect); 499 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 500 VCN, 0, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect); 501 } else { 502 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 503 VCN, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 0, 0, indirect); 504 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 505 VCN, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 0, 0, indirect); 506 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 507 VCN, 0, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect); 508 } 509 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 510 VCN, 0, mmUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE, 0, indirect); 511 512 /* cache window 2: context */ 513 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 514 VCN, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW), 515 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect); 516 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 517 VCN, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH), 518 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect); 519 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 520 VCN, 0, mmUVD_VCPU_CACHE_OFFSET2), 0, 0, indirect); 521 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 522 VCN, 0, mmUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE, 0, indirect); 523 524 /* non-cache window */ 525 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 526 VCN, 0, mmUVD_LMI_VCPU_NC0_64BIT_BAR_LOW), 527 lower_32_bits(adev->vcn.inst[inst_idx].fw_shared_gpu_addr), 0, indirect); 528 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 529 VCN, 0, mmUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH), 530 upper_32_bits(adev->vcn.inst[inst_idx].fw_shared_gpu_addr), 0, indirect); 531 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 532 VCN, 0, mmUVD_VCPU_NONCACHE_OFFSET0), 0, 0, indirect); 533 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 534 VCN, 0, mmUVD_VCPU_NONCACHE_SIZE0), 535 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared)), 0, indirect); 536 537 /* VCN global tiling registers */ 538 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 539 VCN, 0, mmUVD_GFX8_ADDR_CONFIG), adev->gfx.config.gb_addr_config, 0, indirect); 540 } 541 --- 0-DAY CI Kernel Test Service, Intel Corporation https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org