Hi Arnd, I love your patch! Perhaps something to improve: [auto build test WARNING on drm-intel/for-linux-next] [also build test WARNING on v5.11-rc1 next-20201223] [If your patch is applied to the wrong git tree, kindly drop us a note. And when submitting patch, we suggest to use '--base' as documented in https://git-scm.com/docs/git-format-patch] url: https://github.com/0day-ci/linux/commits/Arnd-Bergmann/i915-fix-shift-war... base: git://anongit.freedesktop.org/drm-intel for-linux-next config: x86_64-randconfig-a015-20201230 (attached as .config) compiler: clang version 12.0.0 (https://github.com/llvm/llvm-project 3c0d36f977d9e012b245c796ddc8596ac3af659b) reproduce (this is a W=1 build): wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross chmod +x ~/bin/make.cross # install x86_64 cross compiling tool for clang build # apt-get install binutils-x86-64-linux-gnu # https://github.com/0day-ci/linux/commit/6b837ba40d73c6c02cdf26654c577a901... git remote add linux-review https://github.com/0day-ci/linux git fetch --no-tags linux-review Arnd-Bergmann/i915-fix-shift-warning/20201230-234054 git checkout 6b837ba40d73c6c02cdf26654c577a90130a6b99 # save the attached .config to linux build tree COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross ARCH=x86_64 If you fix the issue, kindly add following tag as appropriate Reported-by: kernel test robot <lkp(a)intel.com&gt; All warnings (new ones prefixed by >>): vdbox_mask, VDBOX_MASK(gt)); ^~~~~~~~~~~~~~ include/drm/drm_print.h:448:48: note: expanded from macro 'drm_dbg' drm_dev_dbg((drm)->dev, DRM_UT_DRIVER, fmt, ##__VA_ARGS__) ~~~ ^~~~~~~~~~~ drivers/gpu/drm/i915/i915_drv.h:1630:2: note: expanded from macro 'VDBOX_MASK' ENGINE_INSTANCES_MASK(gt, VCS0, I915_MAX_VCS) ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/i915/i915_drv.h:1623:49: note: expanded from macro 'ENGINE_INSTANCES_MASK' #define ENGINE_INSTANCES_MASK(gt, first, count) ({ \ ^~~~~~~~~~~~~~~~~ drivers/gpu/drm/i915/gt/intel_engine_cs.c:524:15: warning: format specifies type 'unsigned long' but the argument has type 'unsigned long long' [-Wformat] vebox_mask, VEBOX_MASK(gt)); ^~~~~~~~~~~~~~ include/drm/drm_print.h:448:48: note: expanded from macro 'drm_dbg' drm_dev_dbg((drm)->dev, DRM_UT_DRIVER, fmt, ##__VA_ARGS__) ~~~ ^~~~~~~~~~~ drivers/gpu/drm/i915/i915_drv.h:1632:2: note: expanded from macro 'VEBOX_MASK' ENGINE_INSTANCES_MASK(gt, VECS0, I915_MAX_VECS) ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/i915/i915_drv.h:1623:49: note: expanded from macro 'ENGINE_INSTANCES_MASK' #define ENGINE_INSTANCES_MASK(gt, first, count) ({ \ ^~~~~~~~~~~~~~~~~ 2 warnings generated. vim +509 drivers/gpu/drm/i915/gt/intel_engine_cs.c e26b6d4341476f6 Chris Wilson 2019-12-22 455 f6beb38100778b7 Daniele Ceraolo Spurio 2020-07-07 456 /* f6beb38100778b7 Daniele Ceraolo Spurio 2020-07-07 457 * Determine which engines are fused off in our particular hardware. f6beb38100778b7 Daniele Ceraolo Spurio 2020-07-07 458 * Note that we have a catch-22 situation where we need to be able to access f6beb38100778b7 Daniele Ceraolo Spurio 2020-07-07 459 * the blitter forcewake domain to read the engine fuses, but at the same time f6beb38100778b7 Daniele Ceraolo Spurio 2020-07-07 460 * we need to know which engines are available on the system to know which f6beb38100778b7 Daniele Ceraolo Spurio 2020-07-07 461 * forcewake domains are present. We solve this by intializing the forcewake f6beb38100778b7 Daniele Ceraolo Spurio 2020-07-07 462 * domains based on the full engine mask in the platform capabilities before f6beb38100778b7 Daniele Ceraolo Spurio 2020-07-07 463 * calling this function and pruning the domains for fused-off engines f6beb38100778b7 Daniele Ceraolo Spurio 2020-07-07 464 * afterwards. f6beb38100778b7 Daniele Ceraolo Spurio 2020-07-07 465 */ f6beb38100778b7 Daniele Ceraolo Spurio 2020-07-07 466 static intel_engine_mask_t init_engine_mask(struct intel_gt *gt) f6beb38100778b7 Daniele Ceraolo Spurio 2020-07-07 467 { f6beb38100778b7 Daniele Ceraolo Spurio 2020-07-07 468 struct drm_i915_private *i915 = gt->i915; 792592e72aba416 Daniele Ceraolo Spurio 2020-07-07 469 struct intel_gt_info *info = &gt->info; f6beb38100778b7 Daniele Ceraolo Spurio 2020-07-07 470 struct intel_uncore *uncore = gt->uncore; f6beb38100778b7 Daniele Ceraolo Spurio 2020-07-07 471 unsigned int logical_vdbox = 0; f6beb38100778b7 Daniele Ceraolo Spurio 2020-07-07 472 unsigned int i; f6beb38100778b7 Daniele Ceraolo Spurio 2020-07-07 473 u32 media_fuse; f6beb38100778b7 Daniele Ceraolo Spurio 2020-07-07 474 u16 vdbox_mask; f6beb38100778b7 Daniele Ceraolo Spurio 2020-07-07 475 u16 vebox_mask; f6beb38100778b7 Daniele Ceraolo Spurio 2020-07-07 476 792592e72aba416 Daniele Ceraolo Spurio 2020-07-07 477 info->engine_mask = INTEL_INFO(i915)->platform_engine_mask; 792592e72aba416 Daniele Ceraolo Spurio 2020-07-07 478 f6beb38100778b7 Daniele Ceraolo Spurio 2020-07-07 479 if (INTEL_GEN(i915) < 11) f6beb38100778b7 Daniele Ceraolo Spurio 2020-07-07 480 return info->engine_mask; f6beb38100778b7 Daniele Ceraolo Spurio 2020-07-07 481 f6beb38100778b7 Daniele Ceraolo Spurio 2020-07-07 482 media_fuse = ~intel_uncore_read(uncore, GEN11_GT_VEBOX_VDBOX_DISABLE); f6beb38100778b7 Daniele Ceraolo Spurio 2020-07-07 483 f6beb38100778b7 Daniele Ceraolo Spurio 2020-07-07 484 vdbox_mask = media_fuse & GEN11_GT_VDBOX_DISABLE_MASK; f6beb38100778b7 Daniele Ceraolo Spurio 2020-07-07 485 vebox_mask = (media_fuse & GEN11_GT_VEBOX_DISABLE_MASK) >> f6beb38100778b7 Daniele Ceraolo Spurio 2020-07-07 486 GEN11_GT_VEBOX_DISABLE_SHIFT; f6beb38100778b7 Daniele Ceraolo Spurio 2020-07-07 487 f6beb38100778b7 Daniele Ceraolo Spurio 2020-07-07 488 for (i = 0; i < I915_MAX_VCS; i++) { f6beb38100778b7 Daniele Ceraolo Spurio 2020-07-07 489 if (!HAS_ENGINE(gt, _VCS(i))) { f6beb38100778b7 Daniele Ceraolo Spurio 2020-07-07 490 vdbox_mask &= ~BIT(i); f6beb38100778b7 Daniele Ceraolo Spurio 2020-07-07 491 continue; f6beb38100778b7 Daniele Ceraolo Spurio 2020-07-07 492 } f6beb38100778b7 Daniele Ceraolo Spurio 2020-07-07 493 f6beb38100778b7 Daniele Ceraolo Spurio 2020-07-07 494 if (!(BIT(i) & vdbox_mask)) { f6beb38100778b7 Daniele Ceraolo Spurio 2020-07-07 495 info->engine_mask &= ~BIT(_VCS(i)); f6beb38100778b7 Daniele Ceraolo Spurio 2020-07-07 496 drm_dbg(&i915->drm, "vcs%u fused off\n", i); f6beb38100778b7 Daniele Ceraolo Spurio 2020-07-07 497 continue; f6beb38100778b7 Daniele Ceraolo Spurio 2020-07-07 498 } f6beb38100778b7 Daniele Ceraolo Spurio 2020-07-07 499 f6beb38100778b7 Daniele Ceraolo Spurio 2020-07-07 500 /* f6beb38100778b7 Daniele Ceraolo Spurio 2020-07-07 501 * In Gen11, only even numbered logical VDBOXes are f6beb38100778b7 Daniele Ceraolo Spurio 2020-07-07 502 * hooked up to an SFC (Scaler & Format Converter) unit. f6beb38100778b7 Daniele Ceraolo Spurio 2020-07-07 503 * In TGL each VDBOX has access to an SFC. f6beb38100778b7 Daniele Ceraolo Spurio 2020-07-07 504 */ f6beb38100778b7 Daniele Ceraolo Spurio 2020-07-07 505 if (INTEL_GEN(i915) >= 12 || logical_vdbox++ % 2 == 0) 792592e72aba416 Daniele Ceraolo Spurio 2020-07-07 506 gt->info.vdbox_sfc_access |= BIT(i); f6beb38100778b7 Daniele Ceraolo Spurio 2020-07-07 507 } f6beb38100778b7 Daniele Ceraolo Spurio 2020-07-07 508 drm_dbg(&i915->drm, "vdbox enable: %04x, instances: %04lx\n", f6beb38100778b7 Daniele Ceraolo Spurio 2020-07-07 @509 vdbox_mask, VDBOX_MASK(gt)); f6beb38100778b7 Daniele Ceraolo Spurio 2020-07-07 510 GEM_BUG_ON(vdbox_mask != VDBOX_MASK(gt)); f6beb38100778b7 Daniele Ceraolo Spurio 2020-07-07 511 f6beb38100778b7 Daniele Ceraolo Spurio 2020-07-07 512 for (i = 0; i < I915_MAX_VECS; i++) { f6beb38100778b7 Daniele Ceraolo Spurio 2020-07-07 513 if (!HAS_ENGINE(gt, _VECS(i))) { f6beb38100778b7 Daniele Ceraolo Spurio 2020-07-07 514 vebox_mask &= ~BIT(i); f6beb38100778b7 Daniele Ceraolo Spurio 2020-07-07 515 continue; f6beb38100778b7 Daniele Ceraolo Spurio 2020-07-07 516 } f6beb38100778b7 Daniele Ceraolo Spurio 2020-07-07 517 f6beb38100778b7 Daniele Ceraolo Spurio 2020-07-07 518 if (!(BIT(i) & vebox_mask)) { f6beb38100778b7 Daniele Ceraolo Spurio 2020-07-07 519 info->engine_mask &= ~BIT(_VECS(i)); f6beb38100778b7 Daniele Ceraolo Spurio 2020-07-07 520 drm_dbg(&i915->drm, "vecs%u fused off\n", i); f6beb38100778b7 Daniele Ceraolo Spurio 2020-07-07 521 } f6beb38100778b7 Daniele Ceraolo Spurio 2020-07-07 522 } f6beb38100778b7 Daniele Ceraolo Spurio 2020-07-07 523 drm_dbg(&i915->drm, "vebox enable: %04x, instances: %04lx\n", f6beb38100778b7 Daniele Ceraolo Spurio 2020-07-07 524 vebox_mask, VEBOX_MASK(gt)); f6beb38100778b7 Daniele Ceraolo Spurio 2020-07-07 525 GEM_BUG_ON(vebox_mask != VEBOX_MASK(gt)); f6beb38100778b7 Daniele Ceraolo Spurio 2020-07-07 526 f6beb38100778b7 Daniele Ceraolo Spurio 2020-07-07 527 return info->engine_mask; f6beb38100778b7 Daniele Ceraolo Spurio 2020-07-07 528 } f6beb38100778b7 Daniele Ceraolo Spurio 2020-07-07 529 --- 0-DAY CI Kernel Test Service, Intel Corporation https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org