Hi Alex, First bad commit (maybe != root cause): tree: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git master head: c8c109546a19613d323a319d0c921cb1f317e629 commit: 519607a2f7798decb9c891a4f706aaf780f5a677 drm/amdgpu/display: fold DRM_AMD_DC_DCN201 into DRM_AMD_DC_DCN date: 6 weeks ago config: powerpc64-buildonly-randconfig-r004-20211026 (attached as .config) compiler: powerpc64-linux-gcc (GCC) 11.2.0 reproduce (this is a W=1 build): wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross chmod +x ~/bin/make.cross # https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit... git remote add linus https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git git fetch --no-tags linus master git checkout 519607a2f7798decb9c891a4f706aaf780f5a677 # save the attached .config to linux build tree COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-11.2.0 make.cross ARCH=powerpc If you fix the issue, kindly add following tag as appropriate Reported-by: kernel test robot <lkp(a)intel.com&gt; All warnings (new ones prefixed by >>): 79 | void dcn201_update_clocks_vbios(struct clk_mgr *clk_mgr, | ^~~~~~~~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn201/dcn201_clk_mgr.c: In function 'dcn201_update_clocks': drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn201/dcn201_clk_mgr.c:134:14: warning: variable 'enter_display_off' set but not used [-Wunused-but-set-variable] 134 | bool enter_display_off = false; | ^~~~~~~~~~~~~~~~~ In file included from drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn201/dcn201_clk_mgr.c:38: At top level: drivers/gpu/drm/amd/amdgpu/../include/cyan_skillfish_ip_offset.h:129:29: warning: 'UVD0_BASE' defined but not used [-Wunused-const-variable=] 129 | static const struct IP_BASE UVD0_BASE ={ { { { 0x00007800, 0x00007E00, 0, 0, 0 } }, | ^~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../include/cyan_skillfish_ip_offset.h:123:29: warning: 'UMC0_BASE' defined but not used [-Wunused-const-variable=] 123 | static const struct IP_BASE UMC0_BASE ={ { { { 0x00014000, 0, 0, 0, 0 } }, | ^~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../include/cyan_skillfish_ip_offset.h:117:29: warning: 'THM_BASE' defined but not used [-Wunused-const-variable=] 117 | static const struct IP_BASE THM_BASE ={ { { { 0x00016600, 0, 0, 0, 0 } }, | ^~~~~~~~ drivers/gpu/drm/amd/amdgpu/../include/cyan_skillfish_ip_offset.h:111:29: warning: 'SMUIO_BASE' defined but not used [-Wunused-const-variable=] 111 | static const struct IP_BASE SMUIO_BASE ={ { { { 0x00016800, 0x00016A00, 0, 0, 0 } }, | ^~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../include/cyan_skillfish_ip_offset.h:105:29: warning: 'OSSSYS_BASE' defined but not used [-Wunused-const-variable=] 105 | static const struct IP_BASE OSSSYS_BASE ={ { { { 0x000010A0, 0, 0, 0, 0 } }, | ^~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../include/cyan_skillfish_ip_offset.h:99:29: warning: 'NBIO_BASE' defined but not used [-Wunused-const-variable=] 99 | static const struct IP_BASE NBIO_BASE ={ { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0 } }, | ^~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../include/cyan_skillfish_ip_offset.h:93:29: warning: 'MP1_BASE' defined but not used [-Wunused-const-variable=] 93 | static const struct IP_BASE MP1_BASE ={ { { { 0x00016000, 0, 0, 0, 0 } }, | ^~~~~~~~ drivers/gpu/drm/amd/amdgpu/../include/cyan_skillfish_ip_offset.h:87:29: warning: 'MP0_BASE' defined but not used [-Wunused-const-variable=] 87 | static const struct IP_BASE MP0_BASE ={ { { { 0x00016000, 0, 0, 0, 0 } }, | ^~~~~~~~ drivers/gpu/drm/amd/amdgpu/../include/cyan_skillfish_ip_offset.h:81:29: warning: 'MMHUB_BASE' defined but not used [-Wunused-const-variable=] 81 | static const struct IP_BASE MMHUB_BASE ={ { { { 0x0001A000, 0, 0, 0, 0 } }, | ^~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../include/cyan_skillfish_ip_offset.h:75:29: warning: 'HDP_BASE' defined but not used [-Wunused-const-variable=] 75 | static const struct IP_BASE HDP_BASE ={ { { { 0x00000F20, 0, 0, 0, 0 } }, | ^~~~~~~~ drivers/gpu/drm/amd/amdgpu/../include/cyan_skillfish_ip_offset.h:69:29: warning: 'GC_BASE' defined but not used [-Wunused-const-variable=] 69 | static const struct IP_BASE GC_BASE ={ { { { 0x00001260, 0x0000A000, 0, 0, 0 } }, | ^~~~~~~ drivers/gpu/drm/amd/amdgpu/../include/cyan_skillfish_ip_offset.h:63:29: warning: 'FUSE_BASE' defined but not used [-Wunused-const-variable=] 63 | static const struct IP_BASE FUSE_BASE ={ { { { 0x00017400, 0, 0, 0, 0 } }, | ^~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../include/cyan_skillfish_ip_offset.h:57:29: warning: 'DMU_BASE' defined but not used [-Wunused-const-variable=] 57 | static const struct IP_BASE DMU_BASE ={ { { { 0x00000012, 0x000000C0, 0x000034C0, 0x00009000, 0 } }, | ^~~~~~~~ drivers/gpu/drm/amd/amdgpu/../include/cyan_skillfish_ip_offset.h:51:29: warning: 'DF_BASE' defined but not used [-Wunused-const-variable=] 51 | static const struct IP_BASE DF_BASE ={ { { { 0x00007000, 0, 0, 0, 0 } }, | ^~~~~~~ drivers/gpu/drm/amd/amdgpu/../include/cyan_skillfish_ip_offset.h:45:29: warning: 'CLK_BASE' defined but not used [-Wunused-const-variable=] 45 | static const struct IP_BASE CLK_BASE ={ { { { 0x00016C00, 0, 0, 0, 0 } }, | ^~~~~~~~ drivers/gpu/drm/amd/amdgpu/../include/cyan_skillfish_ip_offset.h:39:29: warning: 'ATHUB_BASE' defined but not used [-Wunused-const-variable=] 39 | static const struct IP_BASE ATHUB_BASE ={ { { { 0x00000C00, 0, 0, 0, 0 } }, | ^~~~~~~~~~ -- 42 | enum dc_irq_source to_dal_irq_source_dcn201( | ^~~~~~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/irq/dcn201/irq_service_dcn201.c:142:43: warning: 'dmub_outbox_irq_info_funcs' defined but not used [-Wunused-const-variable=] 142 | static const struct irq_source_info_funcs dmub_outbox_irq_info_funcs = { | ^~~~~~~~~~~~~~~~~~~~~~~~~~ In file included from drivers/gpu/drm/amd/amdgpu/../display/dc/irq/dcn201/irq_service_dcn201.c:35: drivers/gpu/drm/amd/amdgpu/../include/cyan_skillfish_ip_offset.h:129:29: warning: 'UVD0_BASE' defined but not used [-Wunused-const-variable=] 129 | static const struct IP_BASE UVD0_BASE ={ { { { 0x00007800, 0x00007E00, 0, 0, 0 } }, | ^~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../include/cyan_skillfish_ip_offset.h:123:29: warning: 'UMC0_BASE' defined but not used [-Wunused-const-variable=] 123 | static const struct IP_BASE UMC0_BASE ={ { { { 0x00014000, 0, 0, 0, 0 } }, | ^~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../include/cyan_skillfish_ip_offset.h:117:29: warning: 'THM_BASE' defined but not used [-Wunused-const-variable=] 117 | static const struct IP_BASE THM_BASE ={ { { { 0x00016600, 0, 0, 0, 0 } }, | ^~~~~~~~ drivers/gpu/drm/amd/amdgpu/../include/cyan_skillfish_ip_offset.h:111:29: warning: 'SMUIO_BASE' defined but not used [-Wunused-const-variable=] 111 | static const struct IP_BASE SMUIO_BASE ={ { { { 0x00016800, 0x00016A00, 0, 0, 0 } }, | ^~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../include/cyan_skillfish_ip_offset.h:105:29: warning: 'OSSSYS_BASE' defined but not used [-Wunused-const-variable=] 105 | static const struct IP_BASE OSSSYS_BASE ={ { { { 0x000010A0, 0, 0, 0, 0 } }, | ^~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../include/cyan_skillfish_ip_offset.h:99:29: warning: 'NBIO_BASE' defined but not used [-Wunused-const-variable=] 99 | static const struct IP_BASE NBIO_BASE ={ { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0 } }, | ^~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../include/cyan_skillfish_ip_offset.h:93:29: warning: 'MP1_BASE' defined but not used [-Wunused-const-variable=] 93 | static const struct IP_BASE MP1_BASE ={ { { { 0x00016000, 0, 0, 0, 0 } }, | ^~~~~~~~ drivers/gpu/drm/amd/amdgpu/../include/cyan_skillfish_ip_offset.h:87:29: warning: 'MP0_BASE' defined but not used [-Wunused-const-variable=] 87 | static const struct IP_BASE MP0_BASE ={ { { { 0x00016000, 0, 0, 0, 0 } }, | ^~~~~~~~ drivers/gpu/drm/amd/amdgpu/../include/cyan_skillfish_ip_offset.h:81:29: warning: 'MMHUB_BASE' defined but not used [-Wunused-const-variable=] 81 | static const struct IP_BASE MMHUB_BASE ={ { { { 0x0001A000, 0, 0, 0, 0 } }, | ^~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../include/cyan_skillfish_ip_offset.h:75:29: warning: 'HDP_BASE' defined but not used [-Wunused-const-variable=] 75 | static const struct IP_BASE HDP_BASE ={ { { { 0x00000F20, 0, 0, 0, 0 } }, | ^~~~~~~~ drivers/gpu/drm/amd/amdgpu/../include/cyan_skillfish_ip_offset.h:69:29: warning: 'GC_BASE' defined but not used [-Wunused-const-variable=] 69 | static const struct IP_BASE GC_BASE ={ { { { 0x00001260, 0x0000A000, 0, 0, 0 } }, | ^~~~~~~ drivers/gpu/drm/amd/amdgpu/../include/cyan_skillfish_ip_offset.h:63:29: warning: 'FUSE_BASE' defined but not used [-Wunused-const-variable=] 63 | static const struct IP_BASE FUSE_BASE ={ { { { 0x00017400, 0, 0, 0, 0 } }, | ^~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../include/cyan_skillfish_ip_offset.h:57:29: warning: 'DMU_BASE' defined but not used [-Wunused-const-variable=] 57 | static const struct IP_BASE DMU_BASE ={ { { { 0x00000012, 0x000000C0, 0x000034C0, 0x00009000, 0 } }, | ^~~~~~~~ drivers/gpu/drm/amd/amdgpu/../include/cyan_skillfish_ip_offset.h:51:29: warning: 'DF_BASE' defined but not used [-Wunused-const-variable=] 51 | static const struct IP_BASE DF_BASE ={ { { { 0x00007000, 0, 0, 0, 0 } }, | ^~~~~~~ drivers/gpu/drm/amd/amdgpu/../include/cyan_skillfish_ip_offset.h:45:29: warning: 'CLK_BASE' defined but not used [-Wunused-const-variable=] 45 | static const struct IP_BASE CLK_BASE ={ { { { 0x00016C00, 0, 0, 0, 0 } }, | ^~~~~~~~ drivers/gpu/drm/amd/amdgpu/../include/cyan_skillfish_ip_offset.h:39:29: warning: 'ATHUB_BASE' defined but not used [-Wunused-const-variable=] 39 | static const struct IP_BASE ATHUB_BASE ={ { { { 0x00000C00, 0, 0, 0, 0 } }, | ^~~~~~~~~~ -- 127 | void dcn201_hw_sequencer_construct(struct dc *dc) | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -- In file included from drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:64: 16515 | #define DP_AUX0_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE__SHIFT 0x1f | ^~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_aux.h:213:23: note: in expansion of macro 'DP_AUX0_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE__SHIFT' 213 | .field_name = reg_name ## __ ## field_name ## post_fix | ^~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_aux.h:203:9: note: in expansion of macro 'AUX_SF' 203 | AUX_SF(DP_AUX0_AUX_SW_DATA, AUX_SW_AUTOINCREMENT_DISABLE, mask_sh),\ | ^~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:365:9: note: in expansion of macro 'DCN_AUX_MASK_SH_LIST' 365 | DCN_AUX_MASK_SH_LIST(__SHIFT) | ^~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../include/asic_reg/dcn/dcn_2_0_3_sh_mask.h:16515:111: note: (near initialization for 'aux_shift.AUX_SW_AUTOINCREMENT_DISABLE') 16515 | #define DP_AUX0_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE__SHIFT 0x1f | ^~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_aux.h:213:23: note: in expansion of macro 'DP_AUX0_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE__SHIFT' 213 | .field_name = reg_name ## __ ## field_name ## post_fix | ^~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_aux.h:203:9: note: in expansion of macro 'AUX_SF' 203 | AUX_SF(DP_AUX0_AUX_SW_DATA, AUX_SW_AUTOINCREMENT_DISABLE, mask_sh),\ | ^~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:365:9: note: in expansion of macro 'DCN_AUX_MASK_SH_LIST' 365 | DCN_AUX_MASK_SH_LIST(__SHIFT) | ^~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../include/asic_reg/dcn/dcn_2_0_3_sh_mask.h:16519:111: warning: initialized field overwritten [-Woverride-init] 16519 | #define DP_AUX0_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE_MASK 0x80000000L | ^~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_aux.h:213:23: note: in expansion of macro 'DP_AUX0_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE_MASK' 213 | .field_name = reg_name ## __ ## field_name ## post_fix | ^~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_aux.h:203:9: note: in expansion of macro 'AUX_SF' 203 | AUX_SF(DP_AUX0_AUX_SW_DATA, AUX_SW_AUTOINCREMENT_DISABLE, mask_sh),\ | ^~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:369:9: note: in expansion of macro 'DCN_AUX_MASK_SH_LIST' 369 | DCN_AUX_MASK_SH_LIST(_MASK) | ^~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../include/asic_reg/dcn/dcn_2_0_3_sh_mask.h:16519:111: note: (near initialization for 'aux_mask.AUX_SW_AUTOINCREMENT_DISABLE') 16519 | #define DP_AUX0_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE_MASK 0x80000000L | ^~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_aux.h:213:23: note: in expansion of macro 'DP_AUX0_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE_MASK' 213 | .field_name = reg_name ## __ ## field_name ## post_fix | ^~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_aux.h:203:9: note: in expansion of macro 'AUX_SF' 203 | AUX_SF(DP_AUX0_AUX_SW_DATA, AUX_SW_AUTOINCREMENT_DISABLE, mask_sh),\ | ^~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:369:9: note: in expansion of macro 'DCN_AUX_MASK_SH_LIST' 369 | DCN_AUX_MASK_SH_LIST(_MASK) | ^~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../include/asic_reg/dcn/dcn_2_0_3_sh_mask.h:17500:111: warning: initialized field overwritten [-Woverride-init] 17500 | #define DIG0_TMDS_CTL_BITS__TMDS_CTL0__SHIFT 0x0 | ^~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_link_encoder.h:173:23: note: in expansion of macro 'DIG0_TMDS_CTL_BITS__TMDS_CTL0__SHIFT' 173 | .field_name = reg_name ## __ ## field_name ## post_fix | ^~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_link_encoder.h:184:9: note: in expansion of macro 'LE_SF' 184 | LE_SF(DIG0_TMDS_CTL_BITS, TMDS_CTL0, mask_sh), \ | ^~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:404:9: note: in expansion of macro 'LINK_ENCODER_MASK_SH_LIST_DCN20' 404 | LINK_ENCODER_MASK_SH_LIST_DCN20(mask_sh) | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:407:17: note: in expansion of macro 'LINK_ENCODER_MASK_SH_LIST_DCN201' 407 | LINK_ENCODER_MASK_SH_LIST_DCN201(__SHIFT) | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../include/asic_reg/dcn/dcn_2_0_3_sh_mask.h:17500:111: note: (near initialization for 'le_shift.TMDS_CTL0') 17500 | #define DIG0_TMDS_CTL_BITS__TMDS_CTL0__SHIFT 0x0 | ^~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_link_encoder.h:173:23: note: in expansion of macro 'DIG0_TMDS_CTL_BITS__TMDS_CTL0__SHIFT' 173 | .field_name = reg_name ## __ ## field_name ## post_fix | ^~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_link_encoder.h:184:9: note: in expansion of macro 'LE_SF' 184 | LE_SF(DIG0_TMDS_CTL_BITS, TMDS_CTL0, mask_sh), \ | ^~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:404:9: note: in expansion of macro 'LINK_ENCODER_MASK_SH_LIST_DCN20' 404 | LINK_ENCODER_MASK_SH_LIST_DCN20(mask_sh) | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:407:17: note: in expansion of macro 'LINK_ENCODER_MASK_SH_LIST_DCN201' 407 | LINK_ENCODER_MASK_SH_LIST_DCN201(__SHIFT) | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../include/asic_reg/dcn/dcn_2_0_3_sh_mask.h:17504:111: warning: initialized field overwritten [-Woverride-init] 17504 | #define DIG0_TMDS_CTL_BITS__TMDS_CTL0_MASK 0x00000001L | ^~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_link_encoder.h:173:23: note: in expansion of macro 'DIG0_TMDS_CTL_BITS__TMDS_CTL0_MASK' 173 | .field_name = reg_name ## __ ## field_name ## post_fix | ^~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_link_encoder.h:184:9: note: in expansion of macro 'LE_SF' 184 | LE_SF(DIG0_TMDS_CTL_BITS, TMDS_CTL0, mask_sh), \ | ^~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:404:9: note: in expansion of macro 'LINK_ENCODER_MASK_SH_LIST_DCN20' 404 | LINK_ENCODER_MASK_SH_LIST_DCN20(mask_sh) | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:411:17: note: in expansion of macro 'LINK_ENCODER_MASK_SH_LIST_DCN201' 411 | LINK_ENCODER_MASK_SH_LIST_DCN201(_MASK) | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../include/asic_reg/dcn/dcn_2_0_3_sh_mask.h:17504:111: note: (near initialization for 'le_mask.TMDS_CTL0') 17504 | #define DIG0_TMDS_CTL_BITS__TMDS_CTL0_MASK 0x00000001L | ^~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_link_encoder.h:173:23: note: in expansion of macro 'DIG0_TMDS_CTL_BITS__TMDS_CTL0_MASK' 173 | .field_name = reg_name ## __ ## field_name ## post_fix | ^~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_link_encoder.h:184:9: note: in expansion of macro 'LE_SF' 184 | LE_SF(DIG0_TMDS_CTL_BITS, TMDS_CTL0, mask_sh), \ | ^~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:404:9: note: in expansion of macro 'LINK_ENCODER_MASK_SH_LIST_DCN20' 404 | LINK_ENCODER_MASK_SH_LIST_DCN20(mask_sh) | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:411:17: note: in expansion of macro 'LINK_ENCODER_MASK_SH_LIST_DCN201' 411 | LINK_ENCODER_MASK_SH_LIST_DCN201(_MASK) | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ In file included from drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:61: 247 | #define DMU_BASE__INST0_SEG2 0x000034C0 | ^~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:247:25: note: in expansion of macro 'DMU_BASE__INST0_SEG2' 247 | #define BASE_INNER(seg) DMU_BASE__INST0_SEG ## seg | ^~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:249:19: note: in expansion of macro 'BASE_INNER' 249 | #define BASE(seg) BASE_INNER(seg) | ^~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:256:21: note: in expansion of macro 'BASE' 256 | .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ | ^~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_dpp.h:181:9: note: in expansion of macro 'SRI' 181 | SRI(CURSOR_CONTROL, CURSOR0_, id),\ | ^~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_dpp.h:34:9: note: in expansion of macro 'TF_REG_LIST_DCN20' 34 | TF_REG_LIST_DCN20(id) | ^~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:465:9: note: in expansion of macro 'TF_REG_LIST_DCN201' 465 | TF_REG_LIST_DCN201(id),\ | ^~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:469:9: note: in expansion of macro 'tf_regs' 469 | tf_regs(0), | ^~~~~~~ drivers/gpu/drm/amd/amdgpu/../include/cyan_skillfish_ip_offset.h:247:52: note: (near initialization for 'tf_regs[0].CURSOR_CONTROL') 247 | #define DMU_BASE__INST0_SEG2 0x000034C0 | ^~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:247:25: note: in expansion of macro 'DMU_BASE__INST0_SEG2' 247 | #define BASE_INNER(seg) DMU_BASE__INST0_SEG ## seg | ^~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:249:19: note: in expansion of macro 'BASE_INNER' 249 | #define BASE(seg) BASE_INNER(seg) | ^~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:256:21: note: in expansion of macro 'BASE' 256 | .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ | ^~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_dpp.h:181:9: note: in expansion of macro 'SRI' 181 | SRI(CURSOR_CONTROL, CURSOR0_, id),\ | ^~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_dpp.h:34:9: note: in expansion of macro 'TF_REG_LIST_DCN20' 34 | TF_REG_LIST_DCN20(id) | ^~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:465:9: note: in expansion of macro 'TF_REG_LIST_DCN201' 465 | TF_REG_LIST_DCN201(id),\ | ^~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:469:9: note: in expansion of macro 'tf_regs' 469 | tf_regs(0), | ^~~~~~~ 247 | #define DMU_BASE__INST0_SEG2 0x000034C0 | ^~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:247:25: note: in expansion of macro 'DMU_BASE__INST0_SEG2' 247 | #define BASE_INNER(seg) DMU_BASE__INST0_SEG ## seg | ^~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:249:19: note: in expansion of macro 'BASE_INNER' 249 | #define BASE(seg) BASE_INNER(seg) | ^~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:256:21: note: in expansion of macro 'BASE' 256 | .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ | ^~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_dpp.h:183:9: note: in expansion of macro 'SRI' 183 | SRI(DSCL_MEM_PWR_CTRL, DSCL, id) | ^~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_dpp.h:34:9: note: in expansion of macro 'TF_REG_LIST_DCN20' 34 | TF_REG_LIST_DCN20(id) | ^~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:465:9: note: in expansion of macro 'TF_REG_LIST_DCN201' 465 | TF_REG_LIST_DCN201(id),\ | ^~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:469:9: note: in expansion of macro 'tf_regs' 469 | tf_regs(0), | ^~~~~~~ drivers/gpu/drm/amd/amdgpu/../include/cyan_skillfish_ip_offset.h:247:52: note: (near initialization for 'tf_regs[0].DSCL_MEM_PWR_CTRL') 247 | #define DMU_BASE__INST0_SEG2 0x000034C0 | ^~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:247:25: note: in expansion of macro 'DMU_BASE__INST0_SEG2' 247 | #define BASE_INNER(seg) DMU_BASE__INST0_SEG ## seg | ^~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:249:19: note: in expansion of macro 'BASE_INNER' 249 | #define BASE(seg) BASE_INNER(seg) | ^~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:256:21: note: in expansion of macro 'BASE' 256 | .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ | ^~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_dpp.h:183:9: note: in expansion of macro 'SRI' 183 | SRI(DSCL_MEM_PWR_CTRL, DSCL, id) | ^~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_dpp.h:34:9: note: in expansion of macro 'TF_REG_LIST_DCN20' 34 | TF_REG_LIST_DCN20(id) | ^~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:465:9: note: in expansion of macro 'TF_REG_LIST_DCN201' 465 | TF_REG_LIST_DCN201(id),\ | ^~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:469:9: note: in expansion of macro 'tf_regs' 469 | tf_regs(0), | ^~~~~~~ 247 | #define DMU_BASE__INST0_SEG2 0x000034C0 | ^~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:247:25: note: in expansion of macro 'DMU_BASE__INST0_SEG2' 247 | #define BASE_INNER(seg) DMU_BASE__INST0_SEG ## seg | ^~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:249:19: note: in expansion of macro 'BASE_INNER' 249 | #define BASE(seg) BASE_INNER(seg) | ^~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:256:21: note: in expansion of macro 'BASE' 256 | .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ | ^~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_dpp.h:181:9: note: in expansion of macro 'SRI' 181 | SRI(CURSOR_CONTROL, CURSOR0_, id),\ | ^~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_dpp.h:34:9: note: in expansion of macro 'TF_REG_LIST_DCN20' 34 | TF_REG_LIST_DCN20(id) | ^~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:465:9: note: in expansion of macro 'TF_REG_LIST_DCN201' 465 | TF_REG_LIST_DCN201(id),\ | ^~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:470:9: note: in expansion of macro 'tf_regs' 470 | tf_regs(1), | ^~~~~~~ drivers/gpu/drm/amd/amdgpu/../include/cyan_skillfish_ip_offset.h:247:52: note: (near initialization for 'tf_regs[1].CURSOR_CONTROL') 247 | #define DMU_BASE__INST0_SEG2 0x000034C0 | ^~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:247:25: note: in expansion of macro 'DMU_BASE__INST0_SEG2' 247 | #define BASE_INNER(seg) DMU_BASE__INST0_SEG ## seg | ^~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:249:19: note: in expansion of macro 'BASE_INNER' 249 | #define BASE(seg) BASE_INNER(seg) | ^~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:256:21: note: in expansion of macro 'BASE' 256 | .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ | ^~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_dpp.h:181:9: note: in expansion of macro 'SRI' 181 | SRI(CURSOR_CONTROL, CURSOR0_, id),\ | ^~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_dpp.h:34:9: note: in expansion of macro 'TF_REG_LIST_DCN20' 34 | TF_REG_LIST_DCN20(id) | ^~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:465:9: note: in expansion of macro 'TF_REG_LIST_DCN201' 465 | TF_REG_LIST_DCN201(id),\ | ^~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:470:9: note: in expansion of macro 'tf_regs' 470 | tf_regs(1), | ^~~~~~~ 247 | #define DMU_BASE__INST0_SEG2 0x000034C0 | ^~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:247:25: note: in expansion of macro 'DMU_BASE__INST0_SEG2' 247 | #define BASE_INNER(seg) DMU_BASE__INST0_SEG ## seg | ^~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:249:19: note: in expansion of macro 'BASE_INNER' 249 | #define BASE(seg) BASE_INNER(seg) | ^~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:256:21: note: in expansion of macro 'BASE' 256 | .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ | ^~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_dpp.h:183:9: note: in expansion of macro 'SRI' 183 | SRI(DSCL_MEM_PWR_CTRL, DSCL, id) | ^~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_dpp.h:34:9: note: in expansion of macro 'TF_REG_LIST_DCN20' 34 | TF_REG_LIST_DCN20(id) | ^~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:465:9: note: in expansion of macro 'TF_REG_LIST_DCN201' 465 | TF_REG_LIST_DCN201(id),\ | ^~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:470:9: note: in expansion of macro 'tf_regs' 470 | tf_regs(1), | ^~~~~~~ drivers/gpu/drm/amd/amdgpu/../include/cyan_skillfish_ip_offset.h:247:52: note: (near initialization for 'tf_regs[1].DSCL_MEM_PWR_CTRL') 247 | #define DMU_BASE__INST0_SEG2 0x000034C0 | ^~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:247:25: note: in expansion of macro 'DMU_BASE__INST0_SEG2' 247 | #define BASE_INNER(seg) DMU_BASE__INST0_SEG ## seg | ^~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:249:19: note: in expansion of macro 'BASE_INNER' 249 | #define BASE(seg) BASE_INNER(seg) | ^~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:256:21: note: in expansion of macro 'BASE' 256 | .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ | ^~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_dpp.h:183:9: note: in expansion of macro 'SRI' 183 | SRI(DSCL_MEM_PWR_CTRL, DSCL, id) | ^~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_dpp.h:34:9: note: in expansion of macro 'TF_REG_LIST_DCN20' 34 | TF_REG_LIST_DCN20(id) | ^~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:465:9: note: in expansion of macro 'TF_REG_LIST_DCN201' 465 | TF_REG_LIST_DCN201(id),\ | ^~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:470:9: note: in expansion of macro 'tf_regs' 470 | tf_regs(1), | ^~~~~~~ 247 | #define DMU_BASE__INST0_SEG2 0x000034C0 | ^~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:247:25: note: in expansion of macro 'DMU_BASE__INST0_SEG2' 247 | #define BASE_INNER(seg) DMU_BASE__INST0_SEG ## seg | ^~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:249:19: note: in expansion of macro 'BASE_INNER' 249 | #define BASE(seg) BASE_INNER(seg) | ^~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:256:21: note: in expansion of macro 'BASE' 256 | .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ | ^~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_dpp.h:181:9: note: in expansion of macro 'SRI' 181 | SRI(CURSOR_CONTROL, CURSOR0_, id),\ | ^~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_dpp.h:34:9: note: in expansion of macro 'TF_REG_LIST_DCN20' 34 | TF_REG_LIST_DCN20(id) | ^~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:465:9: note: in expansion of macro 'TF_REG_LIST_DCN201' 465 | TF_REG_LIST_DCN201(id),\ | ^~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:471:9: note: in expansion of macro 'tf_regs' 471 | tf_regs(2), | ^~~~~~~ drivers/gpu/drm/amd/amdgpu/../include/cyan_skillfish_ip_offset.h:247:52: note: (near initialization for 'tf_regs[2].CURSOR_CONTROL') 247 | #define DMU_BASE__INST0_SEG2 0x000034C0 | ^~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:247:25: note: in expansion of macro 'DMU_BASE__INST0_SEG2' 247 | #define BASE_INNER(seg) DMU_BASE__INST0_SEG ## seg | ^~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:249:19: note: in expansion of macro 'BASE_INNER' 249 | #define BASE(seg) BASE_INNER(seg) | ^~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:256:21: note: in expansion of macro 'BASE' 256 | .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ | ^~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_dpp.h:181:9: note: in expansion of macro 'SRI' 181 | SRI(CURSOR_CONTROL, CURSOR0_, id),\ | ^~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_dpp.h:34:9: note: in expansion of macro 'TF_REG_LIST_DCN20' 34 | TF_REG_LIST_DCN20(id) | ^~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:465:9: note: in expansion of macro 'TF_REG_LIST_DCN201' 465 | TF_REG_LIST_DCN201(id),\ | ^~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:471:9: note: in expansion of macro 'tf_regs' 471 | tf_regs(2), | ^~~~~~~ 247 | #define DMU_BASE__INST0_SEG2 0x000034C0 | ^~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:247:25: note: in expansion of macro 'DMU_BASE__INST0_SEG2' 247 | #define BASE_INNER(seg) DMU_BASE__INST0_SEG ## seg | ^~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:249:19: note: in expansion of macro 'BASE_INNER' 249 | #define BASE(seg) BASE_INNER(seg) | ^~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:256:21: note: in expansion of macro 'BASE' 256 | .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ | ^~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_dpp.h:183:9: note: in expansion of macro 'SRI' 183 | SRI(DSCL_MEM_PWR_CTRL, DSCL, id) | ^~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_dpp.h:34:9: note: in expansion of macro 'TF_REG_LIST_DCN20' 34 | TF_REG_LIST_DCN20(id) | ^~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:465:9: note: in expansion of macro 'TF_REG_LIST_DCN201' 465 | TF_REG_LIST_DCN201(id),\ | ^~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:471:9: note: in expansion of macro 'tf_regs' 471 | tf_regs(2), | ^~~~~~~ drivers/gpu/drm/amd/amdgpu/../include/cyan_skillfish_ip_offset.h:247:52: note: (near initialization for 'tf_regs[2].DSCL_MEM_PWR_CTRL') 247 | #define DMU_BASE__INST0_SEG2 0x000034C0 | ^~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:247:25: note: in expansion of macro 'DMU_BASE__INST0_SEG2' 247 | #define BASE_INNER(seg) DMU_BASE__INST0_SEG ## seg | ^~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:249:19: note: in expansion of macro 'BASE_INNER' 249 | #define BASE(seg) BASE_INNER(seg) | ^~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:256:21: note: in expansion of macro 'BASE' 256 | .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ | ^~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_dpp.h:183:9: note: in expansion of macro 'SRI' 183 | SRI(DSCL_MEM_PWR_CTRL, DSCL, id) | ^~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_dpp.h:34:9: note: in expansion of macro 'TF_REG_LIST_DCN20' 34 | TF_REG_LIST_DCN20(id) | ^~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:465:9: note: in expansion of macro 'TF_REG_LIST_DCN201' 465 | TF_REG_LIST_DCN201(id),\ | ^~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:471:9: note: in expansion of macro 'tf_regs' 471 | tf_regs(2), | ^~~~~~~ 247 | #define DMU_BASE__INST0_SEG2 0x000034C0 | ^~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:247:25: note: in expansion of macro 'DMU_BASE__INST0_SEG2' 247 | #define BASE_INNER(seg) DMU_BASE__INST0_SEG ## seg | ^~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:249:19: note: in expansion of macro 'BASE_INNER' 249 | #define BASE(seg) BASE_INNER(seg) | ^~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:256:21: note: in expansion of macro 'BASE' 256 | .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ | ^~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_dpp.h:181:9: note: in expansion of macro 'SRI' 181 | SRI(CURSOR_CONTROL, CURSOR0_, id),\ | ^~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_dpp.h:34:9: note: in expansion of macro 'TF_REG_LIST_DCN20' 34 | TF_REG_LIST_DCN20(id) | ^~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:465:9: note: in expansion of macro 'TF_REG_LIST_DCN201' 465 | TF_REG_LIST_DCN201(id),\ | ^~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:472:9: note: in expansion of macro 'tf_regs' 472 | tf_regs(3), | ^~~~~~~ drivers/gpu/drm/amd/amdgpu/../include/cyan_skillfish_ip_offset.h:247:52: note: (near initialization for 'tf_regs[3].CURSOR_CONTROL') 247 | #define DMU_BASE__INST0_SEG2 0x000034C0 | ^~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:247:25: note: in expansion of macro 'DMU_BASE__INST0_SEG2' 247 | #define BASE_INNER(seg) DMU_BASE__INST0_SEG ## seg | ^~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:249:19: note: in expansion of macro 'BASE_INNER' 249 | #define BASE(seg) BASE_INNER(seg) | ^~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:256:21: note: in expansion of macro 'BASE' 256 | .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ | ^~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_dpp.h:181:9: note: in expansion of macro 'SRI' 181 | SRI(CURSOR_CONTROL, CURSOR0_, id),\ | ^~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_dpp.h:34:9: note: in expansion of macro 'TF_REG_LIST_DCN20' 34 | TF_REG_LIST_DCN20(id) | ^~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:465:9: note: in expansion of macro 'TF_REG_LIST_DCN201' 465 | TF_REG_LIST_DCN201(id),\ | ^~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:472:9: note: in expansion of macro 'tf_regs' 472 | tf_regs(3), | ^~~~~~~ 247 | #define DMU_BASE__INST0_SEG2 0x000034C0 | ^~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:247:25: note: in expansion of macro 'DMU_BASE__INST0_SEG2' 247 | #define BASE_INNER(seg) DMU_BASE__INST0_SEG ## seg | ^~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:249:19: note: in expansion of macro 'BASE_INNER' 249 | #define BASE(seg) BASE_INNER(seg) | ^~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:256:21: note: in expansion of macro 'BASE' 256 | .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ | ^~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_dpp.h:183:9: note: in expansion of macro 'SRI' 183 | SRI(DSCL_MEM_PWR_CTRL, DSCL, id) | ^~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_dpp.h:34:9: note: in expansion of macro 'TF_REG_LIST_DCN20' 34 | TF_REG_LIST_DCN20(id) | ^~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:465:9: note: in expansion of macro 'TF_REG_LIST_DCN201' 465 | TF_REG_LIST_DCN201(id),\ | ^~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:472:9: note: in expansion of macro 'tf_regs' 472 | tf_regs(3), | ^~~~~~~ drivers/gpu/drm/amd/amdgpu/../include/cyan_skillfish_ip_offset.h:247:52: note: (near initialization for 'tf_regs[3].DSCL_MEM_PWR_CTRL') 247 | #define DMU_BASE__INST0_SEG2 0x000034C0 | ^~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:247:25: note: in expansion of macro 'DMU_BASE__INST0_SEG2' 247 | #define BASE_INNER(seg) DMU_BASE__INST0_SEG ## seg | ^~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:249:19: note: in expansion of macro 'BASE_INNER' 249 | #define BASE(seg) BASE_INNER(seg) | ^~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:256:21: note: in expansion of macro 'BASE' 256 | .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ | ^~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_dpp.h:183:9: note: in expansion of macro 'SRI' 183 | SRI(DSCL_MEM_PWR_CTRL, DSCL, id) | ^~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_dpp.h:34:9: note: in expansion of macro 'TF_REG_LIST_DCN20' 34 | TF_REG_LIST_DCN20(id) | ^~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:465:9: note: in expansion of macro 'TF_REG_LIST_DCN201' 465 | TF_REG_LIST_DCN201(id),\ | ^~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:472:9: note: in expansion of macro 'tf_regs' 472 | tf_regs(3), | ^~~~~~~ In file included from drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:64: drivers/gpu/drm/amd/amdgpu/../include/asic_reg/dcn/dcn_2_0_3_sh_mask.h:5596:111: warning: initialized field overwritten [-Woverride-init] 5596 | #define CM0_CM_3DLUT_MODE__CM_3DLUT_MODE__SHIFT 0x0 | ^~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_dpp.h:38:23: note: in expansion of macro 'CM0_CM_3DLUT_MODE__CM_3DLUT_MODE__SHIFT' 38 | .field_name = reg_name ## __ ## field_name ## post_fix | ^~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_dpp.h:368:9: note: in expansion of macro 'TF_SF' 368 | TF_SF(CM0_CM_3DLUT_MODE, CM_3DLUT_MODE, mask_sh), \ | ^~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_dpp.h:547:9: note: in expansion of macro 'TF_REG_LIST_SH_MASK_DCN20_COMMON' 547 | TF_REG_LIST_SH_MASK_DCN20_COMMON(mask_sh), \ | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_dpp.h:37:9: note: in expansion of macro 'TF_REG_LIST_SH_MASK_DCN20' 37 | TF_REG_LIST_SH_MASK_DCN20(mask_sh) | ^~~~~~~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:476:17: note: in expansion of macro 'TF_REG_LIST_SH_MASK_DCN201' 476 | TF_REG_LIST_SH_MASK_DCN201(__SHIFT) | ^~~~~~~~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../include/asic_reg/dcn/dcn_2_0_3_sh_mask.h:5596:111: note: (near initialization for 'tf_shift.CM_3DLUT_MODE') 5596 | #define CM0_CM_3DLUT_MODE__CM_3DLUT_MODE__SHIFT 0x0 | ^~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_dpp.h:38:23: note: in expansion of macro 'CM0_CM_3DLUT_MODE__CM_3DLUT_MODE__SHIFT' 38 | .field_name = reg_name ## __ ## field_name ## post_fix | ^~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_dpp.h:368:9: note: in expansion of macro 'TF_SF' 368 | TF_SF(CM0_CM_3DLUT_MODE, CM_3DLUT_MODE, mask_sh), \ | ^~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_dpp.h:547:9: note: in expansion of macro 'TF_REG_LIST_SH_MASK_DCN20_COMMON' 547 | TF_REG_LIST_SH_MASK_DCN20_COMMON(mask_sh), \ | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_dpp.h:37:9: note: in expansion of macro 'TF_REG_LIST_SH_MASK_DCN20' 37 | TF_REG_LIST_SH_MASK_DCN20(mask_sh) | ^~~~~~~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:476:17: note: in expansion of macro 'TF_REG_LIST_SH_MASK_DCN201' 476 | TF_REG_LIST_SH_MASK_DCN201(__SHIFT) | ^~~~~~~~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../include/asic_reg/dcn/dcn_2_0_3_sh_mask.h:5183:111: warning: initialized field overwritten [-Woverride-init] 5183 | #define CM0_CM_SHAPER_CONTROL__CM_SHAPER_LUT_MODE__SHIFT 0x0 | ^~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_dpp.h:38:23: note: in expansion of macro 'CM0_CM_SHAPER_CONTROL__CM_SHAPER_LUT_MODE__SHIFT' 38 | .field_name = reg_name ## __ ## field_name ## post_fix | ^~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_dpp.h:206:9: note: in expansion of macro 'TF_SF' 206 | TF_SF(CM0_CM_SHAPER_CONTROL, CM_SHAPER_LUT_MODE, mask_sh) | ^~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_dpp.h:548:9: note: in expansion of macro 'TF_REG_LIST_SH_MASK_DCN20_UPDATED' 548 | TF_REG_LIST_SH_MASK_DCN20_UPDATED(mask_sh), \ | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_dpp.h:37:9: note: in expansion of macro 'TF_REG_LIST_SH_MASK_DCN20' 37 | TF_REG_LIST_SH_MASK_DCN20(mask_sh) | ^~~~~~~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:476:17: note: in expansion of macro 'TF_REG_LIST_SH_MASK_DCN201' .. vim +/dcn201_update_clocks_vbios +79 drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn201/dcn201_clk_mgr.c 3f68c01be9a2227 Zhan Liu 2021-09-25 78 3f68c01be9a2227 Zhan Liu 2021-09-25 @79 void dcn201_update_clocks_vbios(struct clk_mgr *clk_mgr, 3f68c01be9a2227 Zhan Liu 2021-09-25 80 struct dc_state *context, 3f68c01be9a2227 Zhan Liu 2021-09-25 81 bool safe_to_lower) 3f68c01be9a2227 Zhan Liu 2021-09-25 82 { 3f68c01be9a2227 Zhan Liu 2021-09-25 83 struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk; 3f68c01be9a2227 Zhan Liu 2021-09-25 84 3f68c01be9a2227 Zhan Liu 2021-09-25 85 bool update_dppclk = false; 3f68c01be9a2227 Zhan Liu 2021-09-25 86 bool update_dispclk = false; 3f68c01be9a2227 Zhan Liu 2021-09-25 87 3f68c01be9a2227 Zhan Liu 2021-09-25 88 if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr->clks.dppclk_khz)) { 3f68c01be9a2227 Zhan Liu 2021-09-25 89 clk_mgr->clks.dppclk_khz = new_clocks->dppclk_khz; 3f68c01be9a2227 Zhan Liu 2021-09-25 90 update_dppclk = true; 3f68c01be9a2227 Zhan Liu 2021-09-25 91 } 3f68c01be9a2227 Zhan Liu 2021-09-25 92 3f68c01be9a2227 Zhan Liu 2021-09-25 93 if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr->clks.dispclk_khz)) { 3f68c01be9a2227 Zhan Liu 2021-09-25 94 clk_mgr->clks.dispclk_khz = new_clocks->dispclk_khz; 3f68c01be9a2227 Zhan Liu 2021-09-25 95 update_dispclk = true; 3f68c01be9a2227 Zhan Liu 2021-09-25 96 } 3f68c01be9a2227 Zhan Liu 2021-09-25 97 3f68c01be9a2227 Zhan Liu 2021-09-25 98 if (update_dppclk || update_dispclk) { 3f68c01be9a2227 Zhan Liu 2021-09-25 99 struct bp_set_dce_clock_parameters dce_clk_params; 3f68c01be9a2227 Zhan Liu 2021-09-25 100 struct dc_bios *bp = clk_mgr->ctx->dc_bios; 3f68c01be9a2227 Zhan Liu 2021-09-25 101 3f68c01be9a2227 Zhan Liu 2021-09-25 102 if (update_dispclk) { 3f68c01be9a2227 Zhan Liu 2021-09-25 103 memset(&dce_clk_params, 0, sizeof(dce_clk_params)); 3f68c01be9a2227 Zhan Liu 2021-09-25 104 dce_clk_params.target_clock_frequency = new_clocks->dispclk_khz; 3f68c01be9a2227 Zhan Liu 2021-09-25 105 dce_clk_params.pll_id = CLOCK_SOURCE_ID_DFS; 3f68c01be9a2227 Zhan Liu 2021-09-25 106 dce_clk_params.clock_type = DCECLOCK_TYPE_DISPLAY_CLOCK; 3f68c01be9a2227 Zhan Liu 2021-09-25 107 bp->funcs->set_dce_clock(bp, &dce_clk_params); 3f68c01be9a2227 Zhan Liu 2021-09-25 108 } 3f68c01be9a2227 Zhan Liu 2021-09-25 109 /* currently there is no DCECLOCK_TYPE_DPPCLK type defined in VBIOS interface. 3f68c01be9a2227 Zhan Liu 2021-09-25 110 * vbios program DPPCLK to the same DispCLK limitation 3f68c01be9a2227 Zhan Liu 2021-09-25 111 */ 3f68c01be9a2227 Zhan Liu 2021-09-25 112 } 3f68c01be9a2227 Zhan Liu 2021-09-25 113 } 3f68c01be9a2227 Zhan Liu 2021-09-25 114 :::::: The code at line 79 was first introduced by commit :::::: 3f68c01be9a2227de1e190317fe34a6fb835a094 drm/amd/display: add cyan_skillfish display support :::::: TO: Zhan Liu <zhan.liu(a)amd.com&gt; :::::: CC: Alex Deucher <alexander.deucher(a)amd.com&gt; --- 0-DAY CI Kernel Test Service, Intel Corporation https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org