Hi Hans, I love your patch! Perhaps something to improve: [auto build test WARNING on pinctrl/devel] [also build test WARNING on v5.8-rc4] [cannot apply to next-20200708] [If your patch is applied to the wrong git tree, kindly drop us a note. And when submitting patch, we suggest to use as documented in https://git-scm.com/docs/git-format-patch] url: https://github.com/0day-ci/linux/commits/Hans-de-Goede/pinctrl-cherryview... base: https://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl.git devel config: x86_64-randconfig-s022-20200709 (attached as .config) compiler: gcc-9 (Debian 9.3.0-14) 9.3.0 reproduce: # apt-get install sparse # sparse version: v0.6.2-37-gc9676a3b-dirty # save the attached .config to linux build tree make W=1 C=1 CF='-fdiagnostic-prefix -D__CHECK_ENDIAN__' ARCH=x86_64 If you fix the issue, kindly add following tag as appropriate Reported-by: kernel test robot <lkp(a)intel.com&gt; sparse warnings: (new ones prefixed by >>) vim +1401 drivers/pinctrl/intel/pinctrl-cherryview.c 1351 1352 static int chv_gpio_irq_type(struct irq_data *d, unsigned int type) 1353 { 1354 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 1355 struct chv_pinctrl *pctrl = gpiochip_get_data(gc); 1356 unsigned int pin = irqd_to_hwirq(d); 1357 unsigned long flags; 1358 u32 value; 1359 1360 raw_spin_lock_irqsave(&chv_lock, flags); 1361 1362 /* 1363 * Pins which can be used as shared interrupt are configured in 1364 * BIOS. Driver trusts BIOS configurations and assigns different 1365 * handler according to the irq type. 1366 * 1367 * Driver needs to save the mapping between each pin and 1368 * its interrupt line. 1369 * 1. If the pin cfg is locked in BIOS: 1370 * Trust BIOS has programmed IntWakeCfg bits correctly, 1371 * driver just needs to save the mapping. 1372 * 2. If the pin cfg is not locked in BIOS: 1373 * Driver programs the IntWakeCfg bits and save the mapping. 1374 */ 1375 if (!chv_pad_locked(pctrl, pin)) { 1376 void __iomem *reg = chv_padreg(pctrl, pin, CHV_PADCTRL1); 1377 1378 value = readl(reg); 1379 value &= ~CHV_PADCTRL1_INTWAKECFG_MASK; 1380 value &= ~CHV_PADCTRL1_INVRXTX_MASK; 1381 1382 if (type & IRQ_TYPE_EDGE_BOTH) { 1383 if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) 1384 value |= CHV_PADCTRL1_INTWAKECFG_BOTH; 1385 else if (type & IRQ_TYPE_EDGE_RISING) 1386 value |= CHV_PADCTRL1_INTWAKECFG_RISING; 1387 else if (type & IRQ_TYPE_EDGE_FALLING) 1388 value |= CHV_PADCTRL1_INTWAKECFG_FALLING; 1389 } else if (type & IRQ_TYPE_LEVEL_MASK) { 1390 value |= CHV_PADCTRL1_INTWAKECFG_LEVEL; 1391 if (type & IRQ_TYPE_LEVEL_LOW) 1392 value |= CHV_PADCTRL1_INVRXTX_RXDATA; 1393 } 1394 1395 chv_writel(value, reg); 1396 } 1397 1398 /* Enable glitch filtering */ 1399 value = readl(chv_padreg(pctrl, pin, CHV_PADCTRL0)); 1400 value |= CHV_PADCTRL0_GLITCH_FILT_BOTH << CHV_PADCTRL0_GLITCH_FILT_SHIFT; 1402 1403 /* Store interrupt-line to pin mapping for this pin*/ 1404 value &= CHV_PADCTRL0_INTSEL_MASK; 1405 value >>= CHV_PADCTRL0_INTSEL_SHIFT; 1406 pctrl->intr_lines[value] = pin; 1407 1408 if (type & IRQ_TYPE_EDGE_BOTH) 1409 irq_set_handler_locked(d, handle_edge_irq); 1410 else if (type & IRQ_TYPE_LEVEL_MASK) 1411 irq_set_handler_locked(d, handle_level_irq); 1412 1413 raw_spin_unlock_irqrestore(&chv_lock, flags); 1414 1415 return 0; 1416 } 1417 --- 0-DAY CI Kernel Test Service, Intel Corporation https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org