tree: https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git master head: 14240d4c5b25d087529691ccf4d7ea256f26cfdf commit: bfefae9f108dfa62eb9c16c9e97086fddb4ece04 [7751/12554] RDMA/hns: Add support for CQ stash config: ia64-randconfig-s032-20201209 (attached as .config) compiler: ia64-linux-gcc (GCC) 9.3.0 reproduce: wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross chmod +x ~/bin/make.cross # apt-get install sparse # sparse version: v0.6.3-179-ga00755aa-dirty # https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/commi... git remote add linux-next https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git git fetch --no-tags linux-next master git checkout bfefae9f108dfa62eb9c16c9e97086fddb4ece04 # save the attached .config to linux build tree COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-9.3.0 make.cross C=1 CF='-fdiagnostic-prefix -D__CHECK_ENDIAN__' ARCH=ia64 If you fix the issue, kindly add following tag as appropriate Reported-by: kernel test robot <lkp(a)intel.com&gt; "sparse warnings: (new ones prefixed by >>)" vim +3172 drivers/infiniband/hw/hns/hns_roce_hw_v2.c 3145 3146 static void hns_roce_v2_write_cqc(struct hns_roce_dev *hr_dev, 3147 struct hns_roce_cq *hr_cq, void *mb_buf, 3148 u64 *mtts, dma_addr_t dma_handle) 3149 { 3150 struct hns_roce_v2_cq_context *cq_context; 3151 3152 cq_context = mb_buf; 3153 memset(cq_context, 0, sizeof(*cq_context)); 3154 3155 roce_set_field(cq_context->byte_4_pg_ceqn, V2_CQC_BYTE_4_CQ_ST_M, 3156 V2_CQC_BYTE_4_CQ_ST_S, V2_CQ_STATE_VALID); 3157 roce_set_field(cq_context->byte_4_pg_ceqn, V2_CQC_BYTE_4_ARM_ST_M, 3158 V2_CQC_BYTE_4_ARM_ST_S, REG_NXT_CEQE); 3159 roce_set_field(cq_context->byte_4_pg_ceqn, V2_CQC_BYTE_4_SHIFT_M, 3160 V2_CQC_BYTE_4_SHIFT_S, ilog2(hr_cq->cq_depth)); 3161 roce_set_field(cq_context->byte_4_pg_ceqn, V2_CQC_BYTE_4_CEQN_M, 3162 V2_CQC_BYTE_4_CEQN_S, hr_cq->vector); 3163 3164 roce_set_field(cq_context->byte_8_cqn, V2_CQC_BYTE_8_CQN_M, 3165 V2_CQC_BYTE_8_CQN_S, hr_cq->cqn); 3166 3167 roce_set_field(cq_context->byte_8_cqn, V2_CQC_BYTE_8_CQE_SIZE_M, 3168 V2_CQC_BYTE_8_CQE_SIZE_S, hr_cq->cqe_size == 3169 HNS_ROCE_V3_CQE_SIZE ? 1 : 0); 3170 3171 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_STASH) 3173 3174 cq_context->cqe_cur_blk_addr = cpu_to_le32(to_hr_hw_page_addr(mtts[0])); 3175 3176 roce_set_field(cq_context->byte_16_hop_addr, 3177 V2_CQC_BYTE_16_CQE_CUR_BLK_ADDR_M, 3178 V2_CQC_BYTE_16_CQE_CUR_BLK_ADDR_S, 3179 upper_32_bits(to_hr_hw_page_addr(mtts[0]))); 3180 roce_set_field(cq_context->byte_16_hop_addr, 3181 V2_CQC_BYTE_16_CQE_HOP_NUM_M, 3182 V2_CQC_BYTE_16_CQE_HOP_NUM_S, hr_dev->caps.cqe_hop_num == 3183 HNS_ROCE_HOP_NUM_0 ? 0 : hr_dev->caps.cqe_hop_num); 3184 3185 cq_context->cqe_nxt_blk_addr = cpu_to_le32(to_hr_hw_page_addr(mtts[1])); 3186 roce_set_field(cq_context->byte_24_pgsz_addr, 3187 V2_CQC_BYTE_24_CQE_NXT_BLK_ADDR_M, 3188 V2_CQC_BYTE_24_CQE_NXT_BLK_ADDR_S, 3189 upper_32_bits(to_hr_hw_page_addr(mtts[1]))); 3190 roce_set_field(cq_context->byte_24_pgsz_addr, 3191 V2_CQC_BYTE_24_CQE_BA_PG_SZ_M, 3192 V2_CQC_BYTE_24_CQE_BA_PG_SZ_S, 3193 to_hr_hw_page_shift(hr_cq->mtr.hem_cfg.ba_pg_shift)); 3194 roce_set_field(cq_context->byte_24_pgsz_addr, 3195 V2_CQC_BYTE_24_CQE_BUF_PG_SZ_M, 3196 V2_CQC_BYTE_24_CQE_BUF_PG_SZ_S, 3197 to_hr_hw_page_shift(hr_cq->mtr.hem_cfg.buf_pg_shift)); 3198 3199 cq_context->cqe_ba = cpu_to_le32(dma_handle >> 3); 3200 3201 roce_set_field(cq_context->byte_40_cqe_ba, V2_CQC_BYTE_40_CQE_BA_M, 3202 V2_CQC_BYTE_40_CQE_BA_S, (dma_handle >> (32 + 3))); 3203 3204 roce_set_bit(cq_context->byte_44_db_record, 3205 V2_CQC_BYTE_44_DB_RECORD_EN_S, 3206 (hr_cq->flags & HNS_ROCE_CQ_FLAG_RECORD_DB) ? 1 : 0); 3207 3208 roce_set_field(cq_context->byte_44_db_record, 3209 V2_CQC_BYTE_44_DB_RECORD_ADDR_M, 3210 V2_CQC_BYTE_44_DB_RECORD_ADDR_S, 3211 ((u32)hr_cq->db.dma) >> 1); 3212 cq_context->db_record_addr = cpu_to_le32(hr_cq->db.dma >> 32); 3213 3214 roce_set_field(cq_context->byte_56_cqe_period_maxcnt, 3215 V2_CQC_BYTE_56_CQ_MAX_CNT_M, 3216 V2_CQC_BYTE_56_CQ_MAX_CNT_S, 3217 HNS_ROCE_V2_CQ_DEFAULT_BURST_NUM); 3218 roce_set_field(cq_context->byte_56_cqe_period_maxcnt, 3219 V2_CQC_BYTE_56_CQ_PERIOD_M, 3220 V2_CQC_BYTE_56_CQ_PERIOD_S, 3221 HNS_ROCE_V2_CQ_DEFAULT_INTERVAL); 3222 } 3223 --- 0-DAY CI Kernel Test Service, Intel Corporation https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org