tree: https://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git pci-dw-config-access head: 28f18b135e96cde3fc59429703fa5844abeacce0 commit: 6a44305151d808c7849efc879c3d0a24af815e50 [9/16] PCI: dwc/tegra: Rework config accesses config: ia64-allmodconfig (attached as .config) compiler: ia64-linux-gcc (GCC) 9.3.0 reproduce (this is a W=1 build): wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross chmod +x ~/bin/make.cross git checkout 6a44305151d808c7849efc879c3d0a24af815e50 # save the attached .config to linux build tree COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-9.3.0 make.cross ARCH=ia64 If you fix the issue, kindly add following tag as appropriate Reported-by: kernel test robot <lkp(a)intel.com&gt; All warnings (new ones prefixed by >>): drivers/pci/controller/dwc/pcie-tegra194.c:604:13: error: 'dw_pcie_own_conf_map_bus' undeclared here (not in a function) 604 | .map_bus = dw_pcie_own_conf_map_bus, | ^~~~~~~~~~~~~~~~~~~~~~~~ drivers/pci/controller/dwc/pcie-tegra194.c: In function 'tegra_pcie_dw_host_init': 975 | pp->bridge->ops = &tegra_pci_ops; | ^ vim +/const +975 drivers/pci/controller/dwc/pcie-tegra194.c 968 969 static int tegra_pcie_dw_host_init(struct pcie_port *pp) 970 { 971 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 972 struct tegra_pcie_dw *pcie = to_tegra_pcie(pci); 973 u32 val, tmp, offset, speed; 974 976 977 tegra_pcie_prepare_host(pp); 978 979 if (dw_pcie_wait_for_link(pci)) { 980 /* 981 * There are some endpoints which can't get the link up if 982 * root port has Data Link Feature (DLF) enabled. 983 * Refer Spec rev 4.0 ver 1.0 sec 3.4.2 & 7.7.4 for more info 984 * on Scaled Flow Control and DLF. 985 * So, need to confirm that is indeed the case here and attempt 986 * link up once again with DLF disabled. 987 */ 988 val = appl_readl(pcie, APPL_DEBUG); 989 val &= APPL_DEBUG_LTSSM_STATE_MASK; 990 val >>= APPL_DEBUG_LTSSM_STATE_SHIFT; 991 tmp = appl_readl(pcie, APPL_LINK_STATUS); 992 tmp &= APPL_LINK_STATUS_RDLH_LINK_UP; 993 if (!(val == 0x11 && !tmp)) { 994 /* Link is down for all good reasons */ 995 return 0; 996 } 997 998 dev_info(pci->dev, "Link is down in DLL"); 999 dev_info(pci->dev, "Trying again with DLFE disabled\n"); 1000 /* Disable LTSSM */ 1001 val = appl_readl(pcie, APPL_CTRL); 1002 val &= ~APPL_CTRL_LTSSM_EN; 1003 appl_writel(pcie, val, APPL_CTRL); 1004 1005 reset_control_assert(pcie->core_rst); 1006 reset_control_deassert(pcie->core_rst); 1007 1008 offset = dw_pcie_find_ext_capability(pci, PCI_EXT_CAP_ID_DLF); 1009 val = dw_pcie_readl_dbi(pci, offset + PCI_DLF_CAP); 1010 val &= ~PCI_DLF_EXCHANGE_ENABLE; 1011 dw_pcie_writel_dbi(pci, offset, val); 1012 1013 tegra_pcie_prepare_host(pp); 1014 1015 if (dw_pcie_wait_for_link(pci)) 1016 return 0; 1017 } 1018 1019 speed = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKSTA) & 1020 PCI_EXP_LNKSTA_CLS; 1021 clk_set_rate(pcie->core_clk, pcie_gen_freq[speed - 1]); 1022 1023 tegra_pcie_enable_interrupts(pp); 1024 1025 return 0; 1026 } 1027 --- 0-DAY CI Kernel Test Service, Intel Corporation https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org