tree: https://github.com/Freescale/linux-fslc pr/296 head: bf2acf9f711d9c0ffcee228f6772f4c00be626b8 commit: fef46455683f097673cd4eef816b185baf141dce [12427/17782] MLK-24206-3 usb: dwc3: core: add fladj setting if SOFITPSYNC used config: i386-randconfig-a003-20210322 (attached as .config) compiler: gcc-9 (Debian 9.3.0-22) 9.3.0 reproduce (this is a W=1 build): # https://github.com/Freescale/linux-fslc/commit/fef46455683f097673cd4eef81... git remote add freescale-fslc https://github.com/Freescale/linux-fslc git fetch --no-tags freescale-fslc pr/296 git checkout fef46455683f097673cd4eef816b185baf141dce # save the attached .config to linux build tree make W=1 ARCH=i386 If you fix the issue, kindly add following tag as appropriate Reported-by: kernel test robot <lkp(a)intel.com&gt; All errors (new ones prefixed by >>): ld: drivers/usb/dwc3/core.o: in function `dwc3_frame_length_adjustment': ld: drivers/usb/cdns3/gadget.o: in function `cdns3_ep_run_transfer': drivers/usb/cdns3/gadget.c:752: undefined reference to `__udivdi3' ld: drivers/usb/cdns3/gadget.o: in function `cdns3_request_handled': drivers/usb/cdns3/gadget.c:889: undefined reference to `__udivdi3' vim +340 drivers/usb/dwc3/core.c 304 305 /* 306 * dwc3_frame_length_adjustment - Adjusts frame length if required 307 * @dwc3: Pointer to our controller context structure 308 */ 309 static void dwc3_frame_length_adjustment(struct dwc3 *dwc) 310 { 311 u32 reg; 312 u32 dft; 313 314 /* 315 * if GCTL.SOFITPSYNC is set to '1': 316 * FLADJ_REF_CLK_FLADJ= 317 * ((125000/ref_clk_period_integer)-(125000/ref_clk_period)) * 318 * ref_clk_period 319 * where 320 * - the ref_clk_period_integer is the integer value of 321 * the ref_clk period got by truncating the decimal (fractional) 322 * value that is programmed in the GUCTL.REF_CLK_PERIOD field. 323 * - the ref_clk_period is the ref_clk period including the fractional 324 * value. 325 */ 326 if (dwc->soft_itp_sync_quirk) { 327 u32 ref_clk_hz, ref_clk_period_integer; 328 u64 temp; 329 330 reg = dwc3_readl(dwc->regs, DWC3_GFLADJ); 331 ref_clk_hz = clk_get_rate(dwc->clks[0].clk); 332 if (ref_clk_hz == 0) { 333 dev_err(dwc->dev, "ref clk is 0, can't set fladj\n"); 334 return; 335 } 336 337 /* nano seconds the period of ref_clk */ 338 ref_clk_period_integer = 1000000000 / ref_clk_hz; 339 temp = 125000L * 1000000000L; 342 temp = temp - 125000; 343 temp = temp << GFLADJ_REFCLK_FLADJ_SHIFT; 344 reg &= ~GFLADJ_REFCLK_FLADJ_MASK; 345 reg |= temp; 346 dwc3_writel(dwc->regs, DWC3_GFLADJ, reg); 347 348 reg = dwc3_readl(dwc->regs, DWC3_GUCTL); 349 reg &= ~DWC3_GUCTL_REFCLKPER_MASK; 350 reg |= ref_clk_period_integer << DWC3_GUCTL_REFCLKPER_SHIFT; 351 dwc3_writel(dwc->regs, DWC3_GUCTL, reg); 352 } 353 354 if (dwc->revision < DWC3_REVISION_250A) 355 return; 356 357 if (dwc->fladj == 0) 358 return; 359 360 reg = dwc3_readl(dwc->regs, DWC3_GFLADJ); 361 dft = reg & DWC3_GFLADJ_30MHZ_MASK; 362 if (dft != dwc->fladj) { 363 reg &= ~DWC3_GFLADJ_30MHZ_MASK; 364 reg |= DWC3_GFLADJ_30MHZ_SDBND_SEL | dwc->fladj; 365 dwc3_writel(dwc->regs, DWC3_GFLADJ, reg); 366 } 367 } 368 --- 0-DAY CI Kernel Test Service, Intel Corporation https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org