tree: https://git.kernel.org/pub/scm/linux/kernel/git/peterz/queue.git x86/fpu head: 374556fa322885f3c7f60b8ca8d249b430c0342f commit: 374556fa322885f3c7f60b8ca8d249b430c0342f [3/3] amdgpu/dc: Annotate __fpu config: powerpc64-randconfig-r011-20210112 (attached as .config) compiler: powerpc64-linux-gcc (GCC) 9.3.0 reproduce (this is a W=1 build): wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross chmod +x ~/bin/make.cross # https://git.kernel.org/pub/scm/linux/kernel/git/peterz/queue.git/commit/?... git remote add peterz-queue https://git.kernel.org/pub/scm/linux/kernel/git/peterz/queue.git git fetch --no-tags peterz-queue x86/fpu git checkout 374556fa322885f3c7f60b8ca8d249b430c0342f # save the attached .config to linux build tree COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-9.3.0 make.cross ARCH=powerpc64 If you fix the issue, kindly add following tag as appropriate Reported-by: kernel test robot <lkp(a)intel.com&gt; All error/warnings (new ones prefixed by >>): 450 | static __fpu void dcn_bw_calc_rq_dlg_ttu( | ^~~~~ | ; 450 | static __fpu void dcn_bw_calc_rq_dlg_ttu( | ^~~~~~~~~~~~~~~~~~~~~~ In file included from drivers/gpu/drm/amd/amdgpu/../display/dc/dm_services_types.h:29, from drivers/gpu/drm/amd/amdgpu/../display/dc/dm_services.h:35, from drivers/gpu/drm/amd/amdgpu/../display/dc/calcs/dcn_calcs.c:27: drivers/gpu/drm/amd/amdgpu/../display/dc/calcs/dcn_calcs.c: In function 'dcn_bw_apply_registry_override': drivers/gpu/drm/amd/amdgpu/../display/dc/os_types.h:68:3: error: implicit declaration of function 'enable_kernel_vsx'; did you mean 'enable_kernel_fp'? [-Werror=implicit-function-declaration] 68 | enable_kernel_vsx(); \ | ^~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/calcs/dcn_calcs.c:638:2: note: in expansion of macro 'DC_FP_START' 638 | DC_FP_START(); | ^~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/os_types.h:79:3: error: implicit declaration of function 'disable_kernel_vsx'; did you mean 'disable_kernel_fp'? [-Werror=implicit-function-declaration] 79 | disable_kernel_vsx(); \ | ^~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/calcs/dcn_calcs.c:674:2: note: in expansion of macro 'DC_FP_END' 674 | DC_FP_END(); | ^~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/calcs/dcn_calcs.c: At top level: drivers/gpu/drm/amd/amdgpu/../display/dc/calcs/dcn_calcs.c:688:13: error: expected ';' before 'void' 688 | static __fpu void hack_force_pipe_split(struct dcn_bw_internal_vars *v, | ^~~~~ | ; 688 | static __fpu void hack_force_pipe_split(struct dcn_bw_internal_vars *v, | ^~~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/calcs/dcn_calcs.c:737:14: warning: no previous prototype for 'get_highest_allowed_voltage_level' [-Wmissing-prototypes] 737 | unsigned int get_highest_allowed_voltage_level(uint32_t chip_family, uint32_t hw_internal_rev, uint32_t pci_revision_id) | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1424 | __fpu unsigned int dcn_find_dcfclk_suits_all( | ^~~~~~~~~ | ; cc1: some warnings being treated as errors vim +/dcn_bw_calc_rq_dlg_ttu +450 drivers/gpu/drm/amd/amdgpu/../display/dc/calcs/dcn_calcs.c 449 451 const struct dc *dc, 452 const struct dcn_bw_internal_vars *v, 453 struct pipe_ctx *pipe, 454 int in_idx) 455 { 456 struct display_mode_lib *dml = (struct display_mode_lib *)(&dc->dml); 457 struct _vcs_dpi_display_dlg_regs_st *dlg_regs = &pipe->dlg_regs; 458 struct _vcs_dpi_display_ttu_regs_st *ttu_regs = &pipe->ttu_regs; 459 struct _vcs_dpi_display_rq_regs_st *rq_regs = &pipe->rq_regs; 460 struct _vcs_dpi_display_rq_params_st rq_param = {0}; 461 struct _vcs_dpi_display_dlg_sys_params_st dlg_sys_param = {0}; 462 struct _vcs_dpi_display_e2e_pipe_params_st input = { { { 0 } } }; 463 float total_active_bw = 0; 464 float total_prefetch_bw = 0; 465 int total_flip_bytes = 0; 466 int i; 467 468 memset(dlg_regs, 0, sizeof(*dlg_regs)); 469 memset(ttu_regs, 0, sizeof(*ttu_regs)); 470 memset(rq_regs, 0, sizeof(*rq_regs)); 471 472 for (i = 0; i < number_of_planes; i++) { 473 total_active_bw += v->read_bandwidth[i]; 474 total_prefetch_bw += v->prefetch_bandwidth[i]; 475 total_flip_bytes += v->total_immediate_flip_bytes[i]; 476 } 477 dlg_sys_param.total_flip_bw = v->return_bw - dcn_bw_max2(total_active_bw, total_prefetch_bw); 478 if (dlg_sys_param.total_flip_bw < 0.0) 479 dlg_sys_param.total_flip_bw = 0; 480 481 dlg_sys_param.t_mclk_wm_us = v->dram_clock_change_watermark; 482 dlg_sys_param.t_sr_wm_us = v->stutter_enter_plus_exit_watermark; 483 dlg_sys_param.t_urg_wm_us = v->urgent_watermark; 484 dlg_sys_param.t_extra_us = v->urgent_extra_latency; 485 dlg_sys_param.deepsleep_dcfclk_mhz = v->dcf_clk_deep_sleep; 486 dlg_sys_param.total_flip_bytes = total_flip_bytes; 487 488 pipe_ctx_to_e2e_pipe_params(pipe, &input.pipe); 489 input.clks_cfg.dcfclk_mhz = v->dcfclk; 490 input.clks_cfg.dispclk_mhz = v->dispclk; 491 input.clks_cfg.dppclk_mhz = v->dppclk; 492 input.clks_cfg.refclk_mhz = dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000.0; 493 input.clks_cfg.socclk_mhz = v->socclk; 494 input.clks_cfg.voltage = v->voltage_level; 495 // dc->dml.logger = pool->base.logger; 496 input.dout.output_format = (v->output_format[in_idx] == dcn_bw_420) ? dm_420 : dm_444; 497 input.dout.output_type = (v->output[in_idx] == dcn_bw_hdmi) ? dm_hdmi : dm_dp; 498 //input[in_idx].dout.output_standard; 499 500 /*todo: soc->sr_enter_plus_exit_time??*/ 501 dlg_sys_param.t_srx_delay_us = dc->dcn_ip->dcfclk_cstate_latency / v->dcf_clk_deep_sleep; 502 503 dml1_rq_dlg_get_rq_params(dml, &rq_param, input.pipe.src); 504 dml1_extract_rq_regs(dml, rq_regs, rq_param); 505 dml1_rq_dlg_get_dlg_params( 506 dml, 507 dlg_regs, 508 ttu_regs, 509 rq_param.dlg, 510 dlg_sys_param, 511 input, 512 true, 513 true, 514 v->pte_enable == dcn_bw_yes, 515 pipe->plane_state->flip_immediate); 516 } 517 --- 0-DAY CI Kernel Test Service, Intel Corporation https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org