tree: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git master head: 704f4cba43d4ed31ef4beb422313f1263d87bc55 commit: 9a3e698c0758ce42059e74998d27d689dadfebc8 drm/amd/display: init soc bounding box for dcn3.01. date: 8 months ago config: i386-randconfig-a013-20200807 (attached as .config) compiler: gcc-9 (Debian 9.3.0-22) 9.3.0 reproduce (this is a W=1 build): # https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit... git remote add linus https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git git fetch --no-tags linus master git checkout 9a3e698c0758ce42059e74998d27d689dadfebc8 # save the attached .config to linux build tree make W=1 ARCH=i386 If you fix the issue, kindly add following tag as appropriate Reported-by: kernel test robot <lkp(a)intel.com&gt; All warnings (new ones prefixed by >>): 999 | struct hubbub *dcn301_hubbub_create(struct dc_context *ctx) | ^~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn301/dcn301_resource.c:1030:26: warning: no previous prototype for 'dcn301_timing_generator_create' [-Wmissing-prototypes] 1030 | struct timing_generator *dcn301_timing_generator_create( | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn301/dcn301_resource.c:1064:22: warning: no previous prototype for 'dcn301_link_encoder_create' [-Wmissing-prototypes] 1064 | struct link_encoder *dcn301_link_encoder_create( | ^~~~~~~~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn301/dcn301_resource.c:1085:20: warning: no previous prototype for 'dcn301_panel_cntl_create' [-Wmissing-prototypes] 1085 | struct panel_cntl *dcn301_panel_cntl_create(const struct panel_cntl_init_data *init_data) | ^~~~~~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn301/dcn301_resource.c:1167:24: warning: no previous prototype for 'dcn301_stream_encoder_create' [-Wmissing-prototypes] 1167 | struct stream_encoder *dcn301_stream_encoder_create( | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn301/dcn301_resource.c:1199:19: warning: no previous prototype for 'dcn301_hwseq_create' [-Wmissing-prototypes] 1199 | struct dce_hwseq *dcn301_hwseq_create( | ^~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn301/dcn301_resource.c:1348:14: warning: no previous prototype for 'dcn301_hubp_create' [-Wmissing-prototypes] 1348 | struct hubp *dcn301_hubp_create( | ^~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn301/dcn301_resource.c:1367:6: warning: no previous prototype for 'dcn301_dwbc_create' [-Wmissing-prototypes] 1367 | bool dcn301_dwbc_create(struct dc_context *ctx, struct resource_pool *pool) | ^~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn301/dcn301_resource.c:1392:6: warning: no previous prototype for 'dcn301_mmhubbub_create' [-Wmissing-prototypes] 1392 | bool dcn301_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool) | ^~~~~~~~~~~~~~~~~~~~~~ In file included from drivers/gpu/drm/amd/amdgpu/../display/dc/dcn301/dcn301_resource.c:66: drivers/gpu/drm/amd/amdgpu/../include/vangogh_ip_offset.h:218:29: warning: 'VCN_BASE' defined but not used [-Wunused-const-variable=] 218 | static const struct IP_BASE VCN_BASE = { { { { 0x00007800, 0x00007E00, 0x02403000, 0, 0, 0 } }, | ^~~~~~~~ drivers/gpu/drm/amd/amdgpu/../include/vangogh_ip_offset.h:210:29: warning: 'USB_BASE' defined but not used [-Wunused-const-variable=] 210 | static const struct IP_BASE USB_BASE = { { { { 0x0242A800, 0x05B00000, 0, 0, 0, 0 } }, | ^~~~~~~~ drivers/gpu/drm/amd/amdgpu/../include/vangogh_ip_offset.h:202:29: warning: 'UMC_BASE' defined but not used [-Wunused-const-variable=] 202 | static const struct IP_BASE UMC_BASE = { { { { 0x00014000, 0x02425800, 0, 0, 0, 0 } }, | ^~~~~~~~ drivers/gpu/drm/amd/amdgpu/../include/vangogh_ip_offset.h:194:29: warning: 'THM_BASE' defined but not used [-Wunused-const-variable=] 194 | static const struct IP_BASE THM_BASE = { { { { 0x00016600, 0x02400C00, 0, 0, 0, 0 } }, | ^~~~~~~~ drivers/gpu/drm/amd/amdgpu/../include/vangogh_ip_offset.h:186:29: warning: 'SMUIO_BASE' defined but not used [-Wunused-const-variable=] 186 | static const struct IP_BASE SMUIO_BASE = { { { { 0x00016800, 0x00016A00, 0x02401000, 0x00440000, 0, 0 } }, | ^~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../include/vangogh_ip_offset.h:178:29: warning: 'PCIE0_BASE' defined but not used [-Wunused-const-variable=] 178 | static const struct IP_BASE PCIE0_BASE = { { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0x0241B000, 0x04040000 } }, | ^~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../include/vangogh_ip_offset.h:170:29: warning: 'OSSSYS_BASE' defined but not used [-Wunused-const-variable=] 170 | static const struct IP_BASE OSSSYS_BASE = { { { { 0x000010A0, 0x0240A000, 0, 0, 0, 0 } }, | ^~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../include/vangogh_ip_offset.h:162:29: warning: 'NBIO_BASE' defined but not used [-Wunused-const-variable=] 162 | static const struct IP_BASE NBIO_BASE = { { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0x0241B000, 0x04040000 } }, | ^~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../include/vangogh_ip_offset.h:154:29: warning: 'MP2_BASE' defined but not used [-Wunused-const-variable=] 154 | static const struct IP_BASE MP2_BASE = { { { { 0x00016400, 0x02400800, 0x00F40000, 0x00F80000, 0x00FC0000, 0 } }, | ^~~~~~~~ drivers/gpu/drm/amd/amdgpu/../include/vangogh_ip_offset.h:146:29: warning: 'MP1_BASE' defined but not used [-Wunused-const-variable=] 146 | static const struct IP_BASE MP1_BASE = { { { { 0x00016000, 0x0243FC00, 0x00DC0000, 0x00E00000, 0x00E40000, 0 } }, | ^~~~~~~~ drivers/gpu/drm/amd/amdgpu/../include/vangogh_ip_offset.h:138:29: warning: 'MP0_BASE' defined but not used [-Wunused-const-variable=] 138 | static const struct IP_BASE MP0_BASE = { { { { 0x00016000, 0x0243FC00, 0x00DC0000, 0x00E00000, 0x00E40000, 0 } }, | ^~~~~~~~ drivers/gpu/drm/amd/amdgpu/../include/vangogh_ip_offset.h:130:29: warning: 'MMHUB_BASE' defined but not used [-Wunused-const-variable=] 130 | static const struct IP_BASE MMHUB_BASE = { { { { 0x00013200, 0x0001A000, 0x02408800, 0, 0, 0 } }, | ^~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../include/vangogh_ip_offset.h:122:29: warning: 'ISP_BASE' defined but not used [-Wunused-const-variable=] 122 | static const struct IP_BASE ISP_BASE = { { { { 0x00018000, 0x0240B000, 0, 0, 0, 0 } }, | ^~~~~~~~ drivers/gpu/drm/amd/amdgpu/../include/vangogh_ip_offset.h:114:29: warning: 'HDP_BASE' defined but not used [-Wunused-const-variable=] 114 | static const struct IP_BASE HDP_BASE = { { { { 0x00000F20, 0x0240A400, 0, 0, 0, 0 } }, | ^~~~~~~~ drivers/gpu/drm/amd/amdgpu/../include/vangogh_ip_offset.h:106:29: warning: 'GC_BASE' defined but not used [-Wunused-const-variable=] 106 | static const struct IP_BASE GC_BASE = { { { { 0x00001260, 0x0000A000, 0x02402C00, 0, 0, 0 } }, | ^~~~~~~ drivers/gpu/drm/amd/amdgpu/../include/vangogh_ip_offset.h:98:29: warning: 'FUSE_BASE' defined but not used [-Wunused-const-variable=] 98 | static const struct IP_BASE FUSE_BASE = { { { { 0x00017400, 0x02401400, 0, 0, 0, 0 } }, | ^~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../include/vangogh_ip_offset.h:90:29: warning: 'FCH_BASE' defined but not used [-Wunused-const-variable=] 90 | static const struct IP_BASE FCH_BASE = { { { { 0x0240C000, 0x00B40000, 0x11000000, 0, 0, 0 } }, | ^~~~~~~~ drivers/gpu/drm/amd/amdgpu/../include/vangogh_ip_offset.h:82:29: warning: 'DPCS_BASE' defined but not used [-Wunused-const-variable=] 82 | static const struct IP_BASE DPCS_BASE = { { { { 0x00000012, 0x000000C0, 0x000034C0, 0x00009000, 0x02403C00, 0 } }, | ^~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../include/vangogh_ip_offset.h:66:29: warning: 'DF_BASE' defined but not used [-Wunused-const-variable=] 66 | static const struct IP_BASE DF_BASE = { { { { 0x00007000, 0x0240B800, 0, 0, 0, 0 } }, | ^~~~~~~ drivers/gpu/drm/amd/amdgpu/../include/vangogh_ip_offset.h:58:29: warning: 'CLK_BASE' defined but not used [-Wunused-const-variable=] 58 | static const struct IP_BASE CLK_BASE = { { { { 0x00016C00, 0x02401800, 0, 0, 0, 0 } }, | ^~~~~~~~ drivers/gpu/drm/amd/amdgpu/../include/vangogh_ip_offset.h:50:29: warning: 'ATHUB_BASE' defined but not used [-Wunused-const-variable=] 50 | static const struct IP_BASE ATHUB_BASE = { { { { 0x00000C00, 0x00013300, 0x02408C00, 0, 0, 0 } }, | ^~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../include/vangogh_ip_offset.h:42:29: warning: 'ACP_BASE' defined but not used [-Wunused-const-variable=] 42 | static const struct IP_BASE ACP_BASE = { { { { 0x02403800, 0x00480000, 0, 0, 0, 0 } }, | ^~~~~~~~ In file included from drivers/gpu/drm/amd/amdgpu/../display/dc/inc/core_types.h:86, from drivers/gpu/drm/amd/amdgpu/../display/dc/inc/resource.h:28, from drivers/gpu/drm/amd/amdgpu/../display/dc/dcn301/dcn301_resource.c:32: drivers/gpu/drm/amd/amdgpu/../display/dc/inc/hw/dpp.h:50:42: warning: 'dpp_input_csc_matrix' defined but not used [-Wunused-const-variable=] 50 | static const struct dpp_input_csc_matrix dpp_input_csc_matrix[] = { | ^~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn301/dcn301_resource.c: In function 'dcn301_update_bw_bounding_box': 1716 | } | ^ vim +1716 drivers/gpu/drm/amd/amdgpu/../display/dc/dcn301/dcn301_resource.c 3a83e4e64bb152 Roman Li 2020-09-29 1663 9a3e698c0758ce Yongqiang Sun 2020-10-08 1664 static void dcn301_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params) 3a83e4e64bb152 Roman Li 2020-09-29 1665 { 9a3e698c0758ce Yongqiang Sun 2020-10-08 1666 struct dcn301_resource_pool *pool = TO_DCN301_RES_POOL(dc->res_pool); 9a3e698c0758ce Yongqiang Sun 2020-10-08 1667 struct clk_limit_table *clk_table = &bw_params->clk_table; 9a3e698c0758ce Yongqiang Sun 2020-10-08 1668 struct _vcs_dpi_voltage_scaling_st clock_limits[DC__VOLTAGE_STATES]; 9a3e698c0758ce Yongqiang Sun 2020-10-08 1669 unsigned int i, closest_clk_lvl; 9a3e698c0758ce Yongqiang Sun 2020-10-08 1670 int j; 9a3e698c0758ce Yongqiang Sun 2020-10-08 1671 9a3e698c0758ce Yongqiang Sun 2020-10-08 1672 // Default clock levels are used for diags, which may lead to overclocking. 9a3e698c0758ce Yongqiang Sun 2020-10-08 1673 if (!IS_DIAG_DC(dc->ctx->dce_environment)) { 9a3e698c0758ce Yongqiang Sun 2020-10-08 1674 dcn3_01_ip.max_num_otg = pool->base.res_cap->num_timing_generator; 9a3e698c0758ce Yongqiang Sun 2020-10-08 1675 dcn3_01_ip.max_num_dpp = pool->base.pipe_count; 9a3e698c0758ce Yongqiang Sun 2020-10-08 1676 dcn3_01_soc.num_chans = bw_params->num_channels; 9a3e698c0758ce Yongqiang Sun 2020-10-08 1677 9a3e698c0758ce Yongqiang Sun 2020-10-08 1678 ASSERT(clk_table->num_entries); 9a3e698c0758ce Yongqiang Sun 2020-10-08 1679 for (i = 0; i < clk_table->num_entries; i++) { 9a3e698c0758ce Yongqiang Sun 2020-10-08 1680 /* loop backwards*/ 9a3e698c0758ce Yongqiang Sun 2020-10-08 1681 for (closest_clk_lvl = 0, j = dcn3_01_soc.num_states - 1; j >= 0; j--) { 9a3e698c0758ce Yongqiang Sun 2020-10-08 1682 if ((unsigned int) dcn3_01_soc.clock_limits[j].dcfclk_mhz <= clk_table->entries[i].dcfclk_mhz) { 9a3e698c0758ce Yongqiang Sun 2020-10-08 1683 closest_clk_lvl = j; 9a3e698c0758ce Yongqiang Sun 2020-10-08 1684 break; 9a3e698c0758ce Yongqiang Sun 2020-10-08 1685 } 9a3e698c0758ce Yongqiang Sun 2020-10-08 1686 } 9a3e698c0758ce Yongqiang Sun 2020-10-08 1687 9a3e698c0758ce Yongqiang Sun 2020-10-08 1688 clock_limits[i].state = i; 9a3e698c0758ce Yongqiang Sun 2020-10-08 1689 clock_limits[i].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz; 9a3e698c0758ce Yongqiang Sun 2020-10-08 1690 clock_limits[i].fabricclk_mhz = clk_table->entries[i].fclk_mhz; 9a3e698c0758ce Yongqiang Sun 2020-10-08 1691 clock_limits[i].socclk_mhz = clk_table->entries[i].socclk_mhz; 9a3e698c0758ce Yongqiang Sun 2020-10-08 1692 clock_limits[i].dram_speed_mts = clk_table->entries[i].memclk_mhz * 2; 9a3e698c0758ce Yongqiang Sun 2020-10-08 1693 9a3e698c0758ce Yongqiang Sun 2020-10-08 1694 clock_limits[i].dispclk_mhz = dcn3_01_soc.clock_limits[closest_clk_lvl].dispclk_mhz; 9a3e698c0758ce Yongqiang Sun 2020-10-08 1695 clock_limits[i].dppclk_mhz = dcn3_01_soc.clock_limits[closest_clk_lvl].dppclk_mhz; 9a3e698c0758ce Yongqiang Sun 2020-10-08 1696 clock_limits[i].dram_bw_per_chan_gbps = dcn3_01_soc.clock_limits[closest_clk_lvl].dram_bw_per_chan_gbps; 9a3e698c0758ce Yongqiang Sun 2020-10-08 1697 clock_limits[i].dscclk_mhz = dcn3_01_soc.clock_limits[closest_clk_lvl].dscclk_mhz; 9a3e698c0758ce Yongqiang Sun 2020-10-08 1698 clock_limits[i].dtbclk_mhz = dcn3_01_soc.clock_limits[closest_clk_lvl].dtbclk_mhz; 9a3e698c0758ce Yongqiang Sun 2020-10-08 1699 clock_limits[i].phyclk_d18_mhz = dcn3_01_soc.clock_limits[closest_clk_lvl].phyclk_d18_mhz; 9a3e698c0758ce Yongqiang Sun 2020-10-08 1700 clock_limits[i].phyclk_mhz = dcn3_01_soc.clock_limits[closest_clk_lvl].phyclk_mhz; 9a3e698c0758ce Yongqiang Sun 2020-10-08 1701 } 9a3e698c0758ce Yongqiang Sun 2020-10-08 1702 for (i = 0; i < clk_table->num_entries; i++) 9a3e698c0758ce Yongqiang Sun 2020-10-08 1703 dcn3_01_soc.clock_limits[i] = clock_limits[i]; 9a3e698c0758ce Yongqiang Sun 2020-10-08 1704 if (clk_table->num_entries) { 9a3e698c0758ce Yongqiang Sun 2020-10-08 1705 dcn3_01_soc.num_states = clk_table->num_entries; 9a3e698c0758ce Yongqiang Sun 2020-10-08 1706 /* duplicate last level */ 9a3e698c0758ce Yongqiang Sun 2020-10-08 1707 dcn3_01_soc.clock_limits[dcn3_01_soc.num_states] = dcn3_01_soc.clock_limits[dcn3_01_soc.num_states - 1]; 9a3e698c0758ce Yongqiang Sun 2020-10-08 1708 dcn3_01_soc.clock_limits[dcn3_01_soc.num_states].state = dcn3_01_soc.num_states; 3a83e4e64bb152 Roman Li 2020-09-29 1709 } 3a83e4e64bb152 Roman Li 2020-09-29 1710 } 3a83e4e64bb152 Roman Li 2020-09-29 1711 3a83e4e64bb152 Roman Li 2020-09-29 1712 dcn3_01_soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0; 3a83e4e64bb152 Roman Li 2020-09-29 1713 dc->dml.soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0; 9a3e698c0758ce Yongqiang Sun 2020-10-08 1714 9a3e698c0758ce Yongqiang Sun 2020-10-08 1715 dml_init_instance(&dc->dml, &dcn3_01_soc, &dcn3_01_ip, DML_PROJECT_DCN30); 3a83e4e64bb152 Roman Li 2020-09-29 @1716 } 3a83e4e64bb152 Roman Li 2020-09-29 1717 :::::: The code at line 1716 was first introduced by commit :::::: 3a83e4e64bb1522ddac67ffc787d1c38291e1a65 drm/amd/display: Add dcn3.01 support to DC (v2) :::::: TO: Roman Li <Roman.Li(a)amd.com&gt; :::::: CC: Alex Deucher <alexander.deucher(a)amd.com&gt; --- 0-DAY CI Kernel Test Service, Intel Corporation https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org