tree: https://github.com/thierryreding/linux for-5.13/work head: 009ea3ee74a12859073a37d2ef800fa154ff7705 commit: 9d6a7689f981eb0ce9c5c6b2a4b5e14d15937815 [42/49] drm/tegra: Support sector layout on Tegra194 config: arm-randconfig-r011-20210318 (attached as .config) compiler: clang version 13.0.0 (https://github.com/llvm/llvm-project fcc1ce00931751ac02498986feb37744e9ace8de) reproduce (this is a W=1 build): wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross chmod +x ~/bin/make.cross # install arm cross compiling tool for clang build # apt-get install binutils-arm-linux-gnueabi # https://github.com/thierryreding/linux/commit/9d6a7689f981eb0ce9c5c6b2a4b... git remote add thierryreding https://github.com/thierryreding/linux git fetch --no-tags thierryreding for-5.13/work git checkout 9d6a7689f981eb0ce9c5c6b2a4b5e14d15937815 # save the attached .config to linux build tree COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross ARCH=arm If you fix the issue, kindly add following tag as appropriate Reported-by: kernel test robot <lkp(a)intel.com&gt; All warnings (new ones prefixed by >>): base |= BIT(39); ^~~~~~~ include/vdso/bits.h:7:26: note: expanded from macro 'BIT' #define BIT(nr) (UL(1) << (nr)) ^ ~~~~ 1 warning generated. vim +512 drivers/gpu/drm/tegra/hub.c 446 447 static void tegra_shared_plane_atomic_update(struct drm_plane *plane, 448 struct drm_atomic_state *state) 449 { 450 struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state, 451 plane); 452 struct tegra_plane_state *tegra_plane_state = to_tegra_plane_state(new_state); 453 struct tegra_dc *dc = to_tegra_dc(new_state->crtc); 454 unsigned int zpos = new_state->normalized_zpos; 455 struct drm_framebuffer *fb = new_state->fb; 456 struct tegra_plane *p = to_tegra_plane(plane); 457 dma_addr_t base; 458 u32 value; 459 int err; 460 461 /* rien ne va plus */ 462 if (!new_state->crtc || !new_state->fb) 463 return; 464 465 if (!new_state->visible) { 466 tegra_shared_plane_atomic_disable(plane, state); 467 return; 468 } 469 470 err = host1x_client_resume(&dc->client); 471 if (err < 0) { 472 dev_err(dc->dev, "failed to resume: %d\n", err); 473 return; 474 } 475 476 tegra_dc_assign_shared_plane(dc, p); 477 478 tegra_plane_writel(p, VCOUNTER, DC_WIN_CORE_ACT_CONTROL); 479 480 /* blending */ 481 value = BLEND_FACTOR_DST_ALPHA_ZERO | BLEND_FACTOR_SRC_ALPHA_K2 | 482 BLEND_FACTOR_DST_COLOR_NEG_K1_TIMES_SRC | 483 BLEND_FACTOR_SRC_COLOR_K1_TIMES_SRC; 484 tegra_plane_writel(p, value, DC_WIN_BLEND_MATCH_SELECT); 485 486 value = BLEND_FACTOR_DST_ALPHA_ZERO | BLEND_FACTOR_SRC_ALPHA_K2 | 487 BLEND_FACTOR_DST_COLOR_NEG_K1_TIMES_SRC | 488 BLEND_FACTOR_SRC_COLOR_K1_TIMES_SRC; 489 tegra_plane_writel(p, value, DC_WIN_BLEND_NOMATCH_SELECT); 490 491 value = K2(255) | K1(255) | WINDOW_LAYER_DEPTH(255 - zpos); 492 tegra_plane_writel(p, value, DC_WIN_BLEND_LAYER_CONTROL); 493 494 /* bypass scaling */ 495 value = HORIZONTAL_TAPS_5 | VERTICAL_TAPS_5; 496 tegra_plane_writel(p, value, DC_WIN_WINDOWGROUP_SET_CONTROL_INPUT_SCALER); 497 498 value = INPUT_SCALER_VBYPASS | INPUT_SCALER_HBYPASS; 499 tegra_plane_writel(p, value, DC_WIN_WINDOWGROUP_SET_INPUT_SCALER_USAGE); 500 501 /* disable compression */ 502 tegra_plane_writel(p, 0, DC_WINBUF_CDE_CONTROL); 503 504 base = tegra_plane_state->iova[0] + fb->offsets[0]; 505 506 /* 507 * Physical address bit 39 in Tegra194 is used as a switch for special 508 * logic that swizzles the memory using either the legacy Tegra or the 509 * dGPU sector layout. 510 */ 511 if (tegra_plane_state->tiling.sector_layout == TEGRA_BO_SECTOR_LAYOUT_GPU) 513 514 tegra_plane_writel(p, tegra_plane_state->format, DC_WIN_COLOR_DEPTH); 515 tegra_plane_writel(p, 0, DC_WIN_PRECOMP_WGRP_PARAMS); 516 517 value = V_POSITION(new_state->crtc_y) | 518 H_POSITION(new_state->crtc_x); 519 tegra_plane_writel(p, value, DC_WIN_POSITION); 520 521 value = V_SIZE(new_state->crtc_h) | H_SIZE(new_state->crtc_w); 522 tegra_plane_writel(p, value, DC_WIN_SIZE); 523 524 value = WIN_ENABLE | COLOR_EXPAND; 525 tegra_plane_writel(p, value, DC_WIN_WIN_OPTIONS); 526 527 value = V_SIZE(new_state->crtc_h) | H_SIZE(new_state->crtc_w); 528 tegra_plane_writel(p, value, DC_WIN_CROPPED_SIZE); 529 530 tegra_plane_writel(p, upper_32_bits(base), DC_WINBUF_START_ADDR_HI); 531 tegra_plane_writel(p, lower_32_bits(base), DC_WINBUF_START_ADDR); 532 533 value = PITCH(fb->pitches[0]); 534 tegra_plane_writel(p, value, DC_WIN_PLANAR_STORAGE); 535 536 value = CLAMP_BEFORE_BLEND | DEGAMMA_SRGB | INPUT_RANGE_FULL; 537 tegra_plane_writel(p, value, DC_WIN_SET_PARAMS); 538 539 value = OFFSET_X(new_state->src_y >> 16) | 540 OFFSET_Y(new_state->src_x >> 16); 541 tegra_plane_writel(p, value, DC_WINBUF_CROPPED_POINT); 542 543 if (dc->soc->supports_block_linear) { 544 unsigned long height = tegra_plane_state->tiling.value; 545 546 /* XXX */ 547 switch (tegra_plane_state->tiling.mode) { 548 case TEGRA_BO_TILING_MODE_PITCH: 549 value = DC_WINBUF_SURFACE_KIND_BLOCK_HEIGHT(0) | 550 DC_WINBUF_SURFACE_KIND_PITCH; 551 break; 552 553 /* XXX not supported on Tegra186 and later */ 554 case TEGRA_BO_TILING_MODE_TILED: 555 value = DC_WINBUF_SURFACE_KIND_TILED; 556 break; 557 558 case TEGRA_BO_TILING_MODE_BLOCK: 559 value = DC_WINBUF_SURFACE_KIND_BLOCK_HEIGHT(height) | 560 DC_WINBUF_SURFACE_KIND_BLOCK; 561 break; 562 } 563 564 tegra_plane_writel(p, value, DC_WINBUF_SURFACE_KIND); 565 } 566 567 /* disable gamut CSC */ 568 value = tegra_plane_readl(p, DC_WIN_WINDOW_SET_CONTROL); 569 value &= ~CONTROL_CSC_ENABLE; 570 tegra_plane_writel(p, value, DC_WIN_WINDOW_SET_CONTROL); 571 572 host1x_client_suspend(&dc->client); 573 } 574 --- 0-DAY CI Kernel Test Service, Intel Corporation https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org