tree: https://github.com/microchip-ung/linux-upstream.git v5.10-webstax head: 0c603c93d534e71ceee9485bfe1b0b75561efb0e commit: 5b4a9de85b60edf37f6322a88a2c37970c81b875 [61/88] mfd: Add sparx5 and jaguar2 PCIe mfd drivers config: x86_64-allyesconfig (attached as .config) compiler: gcc-9 (Debian 9.3.0-15) 9.3.0 reproduce (this is a W=1 build): # https://github.com/microchip-ung/linux-upstream/commit/5b4a9de85b60edf37f... git remote add microchip-ung-linux-upstream https://github.com/microchip-ung/linux-upstream.git git fetch --no-tags microchip-ung-linux-upstream v5.10-webstax git checkout 5b4a9de85b60edf37f6322a88a2c37970c81b875 # save the attached .config to linux build tree make W=1 ARCH=x86_64 If you fix the issue, kindly add following tag as appropriate Reported-by: kernel test robot <lkp(a)intel.com&gt; All warnings (new ones prefixed by >>): drivers/mfd/mscc_jaguar2_pci.c: In function 'jaguar2_pci_probe': 198 | resource_size_t offset; | ^~~~~~ vim +/offset +198 drivers/mfd/mscc_jaguar2_pci.c 192 193 static int jaguar2_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) 194 { 195 struct uio_jaguar2 *priv; 196 struct uio_info *info; 197 int ret; 199 200 if (!pdev->dev.of_node) 201 return -ENODEV; 202 203 ret = pcim_enable_device(pdev); 204 if (ret) 205 return ret; 206 207 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 208 if (ret) { 209 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); 210 if (ret) { 211 dev_err(&pdev->dev, 212 "DMA configuration failed: 0x%x\n", ret); 213 return ret; 214 } 215 } 216 217 offset = pci_resource_start(pdev, JAGUAR2_SWITCH_BAR); 218 219 pci_set_master(pdev); 220 pci_enable_msi(pdev); 221 222 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); 223 if (!priv) 224 return -ENOMEM; 225 226 info = &priv->uio; 227 info->priv = priv; 228 229 iomap = pcim_iomap(pdev, JAGUAR2_SWITCH_BAR, 0); 230 if (!iomap) 231 return -ENOMEM; 232 233 info->mem[0].addr = pci_resource_start(pdev, JAGUAR2_SWITCH_BAR); 234 info->mem[0].size = pci_resource_len(pdev, JAGUAR2_SWITCH_BAR); 235 info->mem[0].memtype = UIO_MEM_PHYS; 236 info->mem[0].internal_addr = iomap; 237 238 info->mem[1].addr = pci_resource_start(pdev, JAGUAR2_CONFIG_BAR); 239 info->mem[1].size = pci_resource_len(pdev, JAGUAR2_CONFIG_BAR); 240 info->mem[1].memtype = UIO_MEM_PHYS; 241 242 info->name = "vcoreiii_switch"; 243 info->version = "0"; 244 info->irq = UIO_IRQ_CUSTOM; 245 info->irqcontrol = jaguar2_irqcontrol; 246 247 spin_lock_init(&priv->lock); 248 priv->flags = 0; /* interrupt is enabled to begin with */ 249 priv->pdev = pdev; 250 251 ret = uio_register_device(&pdev->dev, info); 252 if (ret) 253 return ret; 254 255 pci_set_drvdata(pdev, info); 256 257 dev_info(&pdev->dev, "JAGUAR2: %x\n", 258 (readl(iomap + 0x1010000) >> 12) & 0xffff); 259 260 /* Route IRQs to PCI IRQs (both legacy and MSI) */ 261 writel(0xffffffff, ICPU_INTR_DST_INTR_MAP0 + iomap); 262 writel(0xffffffff, ICPU_INTR_DST_INTR_MAP1 + iomap); 263 writel(0xffffffff, ICPU_INTR_DST_INTR_MAP2 + iomap); 264 writel(0xffffffff, ICPU_INTR_DST_INTR_MAP3 + iomap); 265 writel(ICPU_PCIE_INTR_CFG_INTR_RISING_ENA | 266 ICPU_PCIE_INTR_CFG_INTR_FALLING_ENA, ICPU_PCIE_INTR_CFG0 + 267 iomap); 268 writel(ICPU_PCIE_INTR_CFG_INTR_RISING_ENA | 269 ICPU_PCIE_INTR_CFG_INTR_FALLING_ENA, ICPU_PCIE_INTR_CFG1 + 270 iomap); 271 writel(ICPU_PCIE_INTR_COMMON_CFG_PCIE_INTR_ENA, 272 ICPU_PCIE_INTR_COMMON_CFG + iomap); 273 jaguar2_irq_common_init(pdev, JAGUAR2_NR_IRQ, priv); 274 275 return of_platform_populate(pdev->dev.of_node, NULL, NULL, &pdev->dev); 276 } 277 --- 0-DAY CI Kernel Test Service, Intel Corporation https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org