tree: https://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci.git pci/driver-cleanup head: aa9d693603e587626f4e7835e5a5585defe7d52f commit: 54980de2f55d759e2ee0ba80040f7aa4ccac643c [14/27] PCI: mediatek-gen3: Rename struct mtk_pcie_port to mtk_gen_pcie config: alpha-allyesconfig (https://download.01.org/0day-ci/archive/20211217/202112170916.II7BBAEo-lk...) compiler: alpha-linux-gcc (GCC) 11.2.0 reproduce (this is a W=1 build): wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross chmod +x ~/bin/make.cross # https://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci.git/commit/?i... git remote add helgaas-pci https://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci.git git fetch --no-tags helgaas-pci pci/driver-cleanup git checkout 54980de2f55d759e2ee0ba80040f7aa4ccac643c # save the config file to linux build tree mkdir build_dir COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-11.2.0 make.cross O=build_dir ARCH=alpha SHELL=/bin/bash drivers/pci/controller/ If you fix the issue, kindly add following tag as appropriate Reported-by: kernel test robot <lkp(a)intel.com&gt; All warnings (new ones prefixed by >>): vim +151 drivers/pci/controller/pcie-mediatek-gen3.c 1bdafba538be70 Jianjun Wang 2021-04-20 111 d3bf75b579b980 Jianjun Wang 2021-04-20 112 /** d3bf75b579b980 Jianjun Wang 2021-04-20 113 * struct mtk_pcie_port - PCIe port information d3bf75b579b980 Jianjun Wang 2021-04-20 114 * @dev: pointer to PCIe device d3bf75b579b980 Jianjun Wang 2021-04-20 115 * @base: IO mapped register base d3bf75b579b980 Jianjun Wang 2021-04-20 116 * @reg_base: physical register base d3bf75b579b980 Jianjun Wang 2021-04-20 117 * @mac_reset: MAC reset control d3bf75b579b980 Jianjun Wang 2021-04-20 118 * @phy_reset: PHY reset control d3bf75b579b980 Jianjun Wang 2021-04-20 119 * @phy: PHY controller block d3bf75b579b980 Jianjun Wang 2021-04-20 120 * @clks: PCIe clocks d3bf75b579b980 Jianjun Wang 2021-04-20 121 * @num_clks: PCIe clocks count for this port 814cceebba9b7d Jianjun Wang 2021-04-20 122 * @irq: PCIe controller interrupt number d537dc125f0756 Jianjun Wang 2021-04-20 123 * @saved_irq_state: IRQ enable state saved at suspend time 814cceebba9b7d Jianjun Wang 2021-04-20 124 * @irq_lock: lock protecting IRQ register access 814cceebba9b7d Jianjun Wang 2021-04-20 125 * @intx_domain: legacy INTx IRQ domain 1bdafba538be70 Jianjun Wang 2021-04-20 126 * @msi_domain: MSI IRQ domain 1bdafba538be70 Jianjun Wang 2021-04-20 127 * @msi_bottom_domain: MSI IRQ bottom domain 1bdafba538be70 Jianjun Wang 2021-04-20 128 * @msi_sets: MSI sets information 1bdafba538be70 Jianjun Wang 2021-04-20 129 * @lock: lock protecting IRQ bit map 1bdafba538be70 Jianjun Wang 2021-04-20 130 * @msi_irq_in_use: bit map for assigned MSI IRQ d3bf75b579b980 Jianjun Wang 2021-04-20 131 */ 54980de2f55d75 Fan Fei 2021-11-27 132 struct mtk_gen3_pcie { d3bf75b579b980 Jianjun Wang 2021-04-20 133 struct device *dev; d3bf75b579b980 Jianjun Wang 2021-04-20 134 void __iomem *base; d3bf75b579b980 Jianjun Wang 2021-04-20 135 phys_addr_t reg_base; d3bf75b579b980 Jianjun Wang 2021-04-20 136 struct reset_control *mac_reset; d3bf75b579b980 Jianjun Wang 2021-04-20 137 struct reset_control *phy_reset; d3bf75b579b980 Jianjun Wang 2021-04-20 138 struct phy *phy; d3bf75b579b980 Jianjun Wang 2021-04-20 139 struct clk_bulk_data *clks; d3bf75b579b980 Jianjun Wang 2021-04-20 140 int num_clks; 814cceebba9b7d Jianjun Wang 2021-04-20 141 814cceebba9b7d Jianjun Wang 2021-04-20 142 int irq; d537dc125f0756 Jianjun Wang 2021-04-20 143 u32 saved_irq_state; 814cceebba9b7d Jianjun Wang 2021-04-20 144 raw_spinlock_t irq_lock; 814cceebba9b7d Jianjun Wang 2021-04-20 145 struct irq_domain *intx_domain; 1bdafba538be70 Jianjun Wang 2021-04-20 146 struct irq_domain *msi_domain; 1bdafba538be70 Jianjun Wang 2021-04-20 147 struct irq_domain *msi_bottom_domain; 1bdafba538be70 Jianjun Wang 2021-04-20 148 struct mtk_msi_set msi_sets[PCIE_MSI_SET_NUM]; 1bdafba538be70 Jianjun Wang 2021-04-20 149 struct mutex lock; 1bdafba538be70 Jianjun Wang 2021-04-20 150 DECLARE_BITMAP(msi_irq_in_use, PCIE_MSI_IRQS_NUM); d3bf75b579b980 Jianjun Wang 2021-04-20 @151 }; d3bf75b579b980 Jianjun Wang 2021-04-20 152 :::::: The code at line 151 was first introduced by commit :::::: d3bf75b579b980b9d83a76d3b4d8bfb9f55b24ca PCI: mediatek-gen3: Add MediaTek Gen3 driver for MT8192 :::::: TO: Jianjun Wang <jianjun.wang(a)mediatek.com&gt; :::::: CC: Lorenzo Pieralisi <lorenzo.pieralisi(a)arm.com&gt; --- 0-DAY CI Kernel Test Service, Intel Corporation https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org