Hi Neil, I love your patch! Yet something to improve: [auto build test ERROR on drm-tip/drm-tip] [also build test ERROR on drm-exynos/exynos-drm-next tegra-drm/drm/tegra/for-next v5.16 next-20220120] [cannot apply to drm/drm-next drm-intel/for-linux-next airlied/drm-next] [If your patch is applied to the wrong git tree, kindly drop us a note. And when submitting patch, we suggest to use '--base' as documented in https://git-scm.com/docs/git-format-patch] url: https://github.com/0day-ci/linux/commits/Neil-Armstrong/drm-meson-add-sup... base: git://anongit.freedesktop.org/drm/drm-tip drm-tip config: arm64-buildonly-randconfig-r005-20220120 (https://download.01.org/0day-ci/archive/20220120/202201202318.BaTOOAWE-lk...) compiler: aarch64-linux-gcc (GCC) 11.2.0 reproduce (this is a W=1 build): wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross chmod +x ~/bin/make.cross # https://github.com/0day-ci/linux/commit/582fe216b10e102620e7148d6df969d4e... git remote add linux-review https://github.com/0day-ci/linux git fetch --no-tags linux-review Neil-Armstrong/drm-meson-add-support-for-MIPI-DSI-Display/20220120-163607 git checkout 582fe216b10e102620e7148d6df969d4eed430af # save the config file to linux build tree mkdir build_dir COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-11.2.0 make.cross O=build_dir ARCH=arm64 SHELL=/bin/bash drivers/gpu/drm/meson/ If you fix the issue, kindly add following tag as appropriate Reported-by: kernel test robot <lkp(a)intel.com&gt; All errors (new ones prefixed by >>): In file included from include/linux/swab.h:5, from include/uapi/linux/byteorder/big_endian.h:14, from include/linux/byteorder/big_endian.h:5, from arch/arm64/include/uapi/asm/byteorder.h:21, from include/asm-generic/bitops/le.h:7, from arch/arm64/include/asm/bitops.h:29, from include/linux/bitops.h:33, from include/linux/kernel.h:13, from include/linux/iopoll.h:9, from drivers/gpu/drm/meson/meson_venc.c:9: drivers/gpu/drm/meson/meson_venc.c: In function 'meson_venc_mipi_dsi_mode_set': 1661 | writel_relaxed(ENCL_PX_LN_CNT_SHADOW_EN, priv->io_base + _REG(ENCL_VIDEO_MODE)); | ^~~~~~~~~~~~~~~~~~~~~~~~ include/uapi/linux/swab.h:118:39: note: in definition of macro '__swab32' 118 | (__builtin_constant_p((__u32)(x)) ? \ | ^ include/linux/byteorder/generic.h:88:21: note: in expansion of macro '__cpu_to_le32' 88 | #define cpu_to_le32 __cpu_to_le32 | ^~~~~~~~~~~~~ drivers/gpu/drm/meson/meson_venc.c:1661:9: note: in expansion of macro 'writel_relaxed' 1661 | writel_relaxed(ENCL_PX_LN_CNT_SHADOW_EN, priv->io_base + _REG(ENCL_VIDEO_MODE)); | ^~~~~~~~~~~~~~ drivers/gpu/drm/meson/meson_venc.c:1661:24: note: each undeclared identifier is reported only once for each function it appears in 1661 | writel_relaxed(ENCL_PX_LN_CNT_SHADOW_EN, priv->io_base + _REG(ENCL_VIDEO_MODE)); | ^~~~~~~~~~~~~~~~~~~~~~~~ include/uapi/linux/swab.h:118:39: note: in definition of macro '__swab32' 118 | (__builtin_constant_p((__u32)(x)) ? \ | ^ include/linux/byteorder/generic.h:88:21: note: in expansion of macro '__cpu_to_le32' 88 | #define cpu_to_le32 __cpu_to_le32 | ^~~~~~~~~~~~~ drivers/gpu/drm/meson/meson_venc.c:1661:9: note: in expansion of macro 'writel_relaxed' 1661 | writel_relaxed(ENCL_PX_LN_CNT_SHADOW_EN, priv->io_base + _REG(ENCL_VIDEO_MODE)); | ^~~~~~~~~~~~~~ 1662 | writel_relaxed(ENCL_VIDEO_MODE_ADV_VFIFO_EN | | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~ include/uapi/linux/swab.h:118:39: note: in definition of macro '__swab32' 118 | (__builtin_constant_p((__u32)(x)) ? \ | ^ include/linux/byteorder/generic.h:88:21: note: in expansion of macro '__cpu_to_le32' 88 | #define cpu_to_le32 __cpu_to_le32 | ^~~~~~~~~~~~~ drivers/gpu/drm/meson/meson_venc.c:1662:9: note: in expansion of macro 'writel_relaxed' 1662 | writel_relaxed(ENCL_VIDEO_MODE_ADV_VFIFO_EN | | ^~~~~~~~~~~~~~ 1663 | ENCL_VIDEO_MODE_ADV_GAIN_HDTV | | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~ include/uapi/linux/swab.h:118:39: note: in definition of macro '__swab32' 118 | (__builtin_constant_p((__u32)(x)) ? \ | ^ include/linux/byteorder/generic.h:88:21: note: in expansion of macro '__cpu_to_le32' 88 | #define cpu_to_le32 __cpu_to_le32 | ^~~~~~~~~~~~~ drivers/gpu/drm/meson/meson_venc.c:1662:9: note: in expansion of macro 'writel_relaxed' 1662 | writel_relaxed(ENCL_VIDEO_MODE_ADV_VFIFO_EN | | ^~~~~~~~~~~~~~ 1664 | ENCL_SEL_GAMMA_RGB_IN, priv->io_base + _REG(ENCL_VIDEO_MODE_ADV)); | ^~~~~~~~~~~~~~~~~~~~~ include/uapi/linux/swab.h:118:39: note: in definition of macro '__swab32' 118 | (__builtin_constant_p((__u32)(x)) ? \ | ^ include/linux/byteorder/generic.h:88:21: note: in expansion of macro '__cpu_to_le32' 88 | #define cpu_to_le32 __cpu_to_le32 | ^~~~~~~~~~~~~ drivers/gpu/drm/meson/meson_venc.c:1662:9: note: in expansion of macro 'writel_relaxed' 1662 | writel_relaxed(ENCL_VIDEO_MODE_ADV_VFIFO_EN | | ^~~~~~~~~~~~~~ 1666 | writel_relaxed(ENCL_VIDEO_FILT_CTRL_BYPASS_FILTER, | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ include/uapi/linux/swab.h:118:39: note: in definition of macro '__swab32' 118 | (__builtin_constant_p((__u32)(x)) ? \ | ^ include/linux/byteorder/generic.h:88:21: note: in expansion of macro '__cpu_to_le32' 88 | #define cpu_to_le32 __cpu_to_le32 | ^~~~~~~~~~~~~ drivers/gpu/drm/meson/meson_venc.c:1666:9: note: in expansion of macro 'writel_relaxed' 1666 | writel_relaxed(ENCL_VIDEO_FILT_CTRL_BYPASS_FILTER, | ^~~~~~~~~~~~~~ 1681 | writel_relaxed(ENCL_VIDEO_RGBIN_RGB | ENCL_VIDEO_RGBIN_ZBLK, | ^~~~~~~~~~~~~~~~~~~~ include/uapi/linux/swab.h:118:39: note: in definition of macro '__swab32' 118 | (__builtin_constant_p((__u32)(x)) ? \ | ^ include/linux/byteorder/generic.h:88:21: note: in expansion of macro '__cpu_to_le32' 88 | #define cpu_to_le32 __cpu_to_le32 | ^~~~~~~~~~~~~ drivers/gpu/drm/meson/meson_venc.c:1681:9: note: in expansion of macro 'writel_relaxed' 1681 | writel_relaxed(ENCL_VIDEO_RGBIN_RGB | ENCL_VIDEO_RGBIN_ZBLK, | ^~~~~~~~~~~~~~ 1681 | writel_relaxed(ENCL_VIDEO_RGBIN_RGB | ENCL_VIDEO_RGBIN_ZBLK, | ^~~~~~~~~~~~~~~~~~~~~ include/uapi/linux/swab.h:118:39: note: in definition of macro '__swab32' 118 | (__builtin_constant_p((__u32)(x)) ? \ | ^ include/linux/byteorder/generic.h:88:21: note: in expansion of macro '__cpu_to_le32' 88 | #define cpu_to_le32 __cpu_to_le32 | ^~~~~~~~~~~~~ drivers/gpu/drm/meson/meson_venc.c:1681:9: note: in expansion of macro 'writel_relaxed' 1681 | writel_relaxed(ENCL_VIDEO_RGBIN_RGB | ENCL_VIDEO_RGBIN_ZBLK, | ^~~~~~~~~~~~~~ 1753 | writel_relaxed(L_TCON_MISC_SEL_STV1 | L_TCON_MISC_SEL_STV2, | ^~~~~~~~~~~~~~~~~~~~ include/uapi/linux/swab.h:118:39: note: in definition of macro '__swab32' 118 | (__builtin_constant_p((__u32)(x)) ? \ | ^ include/linux/byteorder/generic.h:88:21: note: in expansion of macro '__cpu_to_le32' 88 | #define cpu_to_le32 __cpu_to_le32 | ^~~~~~~~~~~~~ drivers/gpu/drm/meson/meson_venc.c:1753:9: note: in expansion of macro 'writel_relaxed' 1753 | writel_relaxed(L_TCON_MISC_SEL_STV1 | L_TCON_MISC_SEL_STV2, | ^~~~~~~~~~~~~~ 1753 | writel_relaxed(L_TCON_MISC_SEL_STV1 | L_TCON_MISC_SEL_STV2, | ^~~~~~~~~~~~~~~~~~~~ include/uapi/linux/swab.h:118:39: note: in definition of macro '__swab32' 118 | (__builtin_constant_p((__u32)(x)) ? \ | ^ include/linux/byteorder/generic.h:88:21: note: in expansion of macro '__cpu_to_le32' 88 | #define cpu_to_le32 __cpu_to_le32 | ^~~~~~~~~~~~~ drivers/gpu/drm/meson/meson_venc.c:1753:9: note: in expansion of macro 'writel_relaxed' 1753 | writel_relaxed(L_TCON_MISC_SEL_STV1 | L_TCON_MISC_SEL_STV2, | ^~~~~~~~~~~~~~ drivers/gpu/drm/meson/meson_venc.c: In function 'meson_venc_enable_vsync': 1952 | writel_relaxed(VENC_INTCTRL_ENCP_LNRST_INT_EN, | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ include/uapi/linux/swab.h:118:39: note: in definition of macro '__swab32' 118 | (__builtin_constant_p((__u32)(x)) ? \ | ^ include/linux/byteorder/generic.h:88:21: note: in expansion of macro '__cpu_to_le32' 88 | #define cpu_to_le32 __cpu_to_le32 | ^~~~~~~~~~~~~ drivers/gpu/drm/meson/meson_venc.c:1952:17: note: in expansion of macro 'writel_relaxed' 1952 | writel_relaxed(VENC_INTCTRL_ENCP_LNRST_INT_EN, | ^~~~~~~~~~~~~~ vim +/ENCL_PX_LN_CNT_SHADOW_EN +1661 drivers/gpu/drm/meson/meson_venc.c 1627 1628 void meson_venc_mipi_dsi_mode_set(struct meson_drm *priv, 1629 const struct drm_display_mode *mode) 1630 { 1631 unsigned int max_pxcnt; 1632 unsigned int max_lncnt; 1633 unsigned int havon_begin; 1634 unsigned int havon_end; 1635 unsigned int vavon_bline; 1636 unsigned int vavon_eline; 1637 unsigned int hso_begin; 1638 unsigned int hso_end; 1639 unsigned int vso_begin; 1640 unsigned int vso_end; 1641 unsigned int vso_bline; 1642 unsigned int vso_eline; 1643 1644 max_pxcnt = mode->htotal - 1; 1645 max_lncnt = mode->vtotal - 1; 1646 havon_begin = mode->htotal - mode->hsync_start; 1647 havon_end = havon_begin + mode->hdisplay - 1; 1648 vavon_bline = mode->vtotal - mode->vsync_start; 1649 vavon_eline = vavon_bline + mode->vdisplay - 1; 1650 hso_begin = 0; 1651 hso_end = mode->hsync_end - mode->hsync_start; 1652 vso_begin = 0; 1653 vso_end = 0; 1654 vso_bline = 0; 1655 vso_eline = mode->vsync_end - mode->vsync_start; 1656 1657 meson_vpp_setup_mux(priv, MESON_VIU_VPP_MUX_ENCL); 1658 1659 writel_relaxed(0, priv->io_base + _REG(ENCL_VIDEO_EN)); 1660 1665 1667 priv->io_base + _REG(ENCL_VIDEO_FILT_CTRL)); 1668 writel_relaxed(max_pxcnt, priv->io_base + _REG(ENCL_VIDEO_MAX_PXCNT)); 1669 writel_relaxed(max_lncnt, priv->io_base + _REG(ENCL_VIDEO_MAX_LNCNT)); 1670 writel_relaxed(havon_begin, priv->io_base + _REG(ENCL_VIDEO_HAVON_BEGIN)); 1671 writel_relaxed(havon_end, priv->io_base + _REG(ENCL_VIDEO_HAVON_END)); 1672 writel_relaxed(vavon_bline, priv->io_base + _REG(ENCL_VIDEO_VAVON_BLINE)); 1673 writel_relaxed(vavon_eline, priv->io_base + _REG(ENCL_VIDEO_VAVON_ELINE)); 1674 1675 writel_relaxed(hso_begin, priv->io_base + _REG(ENCL_VIDEO_HSO_BEGIN)); 1676 writel_relaxed(hso_end, priv->io_base + _REG(ENCL_VIDEO_HSO_END)); 1677 writel_relaxed(vso_begin, priv->io_base + _REG(ENCL_VIDEO_VSO_BEGIN)); 1678 writel_relaxed(vso_end, priv->io_base + _REG(ENCL_VIDEO_VSO_END)); 1679 writel_relaxed(vso_bline, priv->io_base + _REG(ENCL_VIDEO_VSO_BLINE)); 1680 writel_relaxed(vso_eline, priv->io_base + _REG(ENCL_VIDEO_VSO_ELINE)); 1682 priv->io_base + _REG(ENCL_VIDEO_RGBIN_CTRL)); 1683 1684 /* default black pattern */ 1685 writel_relaxed(0, priv->io_base + _REG(ENCL_TST_MDSEL)); 1686 writel_relaxed(0, priv->io_base + _REG(ENCL_TST_Y)); 1687 writel_relaxed(0, priv->io_base + _REG(ENCL_TST_CB)); 1688 writel_relaxed(0, priv->io_base + _REG(ENCL_TST_CR)); 1689 writel_relaxed(1, priv->io_base + _REG(ENCL_TST_EN)); 1690 writel_bits_relaxed(ENCL_VIDEO_MODE_ADV_VFIFO_EN, 0, 1691 priv->io_base + _REG(ENCL_VIDEO_MODE_ADV)); 1692 1693 writel_relaxed(1, priv->io_base + _REG(ENCL_VIDEO_EN)); 1694 1695 writel_relaxed(0, priv->io_base + _REG(L_RGB_BASE_ADDR)); 1696 writel_relaxed(0x400, priv->io_base + _REG(L_RGB_COEFF_ADDR)); /* Magic value */ 1697 1698 writel_relaxed(L_DITH_CNTL_DITH10_EN, priv->io_base + _REG(L_DITH_CNTL_ADDR)); 1699 1700 /* DE signal for TTL */ 1701 writel_relaxed(havon_begin, priv->io_base + _REG(L_OEH_HS_ADDR)); 1702 writel_relaxed(havon_end + 1, priv->io_base + _REG(L_OEH_HE_ADDR)); 1703 writel_relaxed(vavon_bline, priv->io_base + _REG(L_OEH_VS_ADDR)); 1704 writel_relaxed(vavon_eline, priv->io_base + _REG(L_OEH_VE_ADDR)); 1705 1706 /* DE signal for TTL */ 1707 writel_relaxed(havon_begin, priv->io_base + _REG(L_OEV1_HS_ADDR)); 1708 writel_relaxed(havon_end + 1, priv->io_base + _REG(L_OEV1_HE_ADDR)); 1709 writel_relaxed(vavon_bline, priv->io_base + _REG(L_OEV1_VS_ADDR)); 1710 writel_relaxed(vavon_eline, priv->io_base + _REG(L_OEV1_VE_ADDR)); 1711 1712 /* Hsync signal for TTL */ 1713 if (mode->flags & DRM_MODE_FLAG_PHSYNC) { 1714 writel_relaxed(hso_end, priv->io_base + _REG(L_STH1_HS_ADDR)); 1715 writel_relaxed(hso_begin, priv->io_base + _REG(L_STH1_HE_ADDR)); 1716 } else { 1717 writel_relaxed(hso_begin, priv->io_base + _REG(L_STH1_HS_ADDR)); 1718 writel_relaxed(hso_end, priv->io_base + _REG(L_STH1_HE_ADDR)); 1719 } 1720 writel_relaxed(0, priv->io_base + _REG(L_STH1_VS_ADDR)); 1721 writel_relaxed(max_lncnt, priv->io_base + _REG(L_STH1_VE_ADDR)); 1722 1723 /* Vsync signal for TTL */ 1724 writel_relaxed(vso_begin, priv->io_base + _REG(L_STV1_HS_ADDR)); 1725 writel_relaxed(vso_end, priv->io_base + _REG(L_STV1_HE_ADDR)); 1726 if (mode->flags & DRM_MODE_FLAG_PVSYNC) { 1727 writel_relaxed(vso_eline, priv->io_base + _REG(L_STV1_VS_ADDR)); 1728 writel_relaxed(vso_bline, priv->io_base + _REG(L_STV1_VE_ADDR)); 1729 } else { 1730 writel_relaxed(vso_bline, priv->io_base + _REG(L_STV1_VS_ADDR)); 1731 writel_relaxed(vso_eline, priv->io_base + _REG(L_STV1_VE_ADDR)); 1732 } 1733 1734 /* DE signal */ 1735 writel_relaxed(havon_begin, priv->io_base + _REG(L_DE_HS_ADDR)); 1736 writel_relaxed(havon_end + 1, priv->io_base + _REG(L_DE_HE_ADDR)); 1737 writel_relaxed(vavon_bline, priv->io_base + _REG(L_DE_VS_ADDR)); 1738 writel_relaxed(vavon_eline, priv->io_base + _REG(L_DE_VE_ADDR)); 1739 1740 /* Hsync signal */ 1741 writel_relaxed(hso_begin, priv->io_base + _REG(L_HSYNC_HS_ADDR)); 1742 writel_relaxed(hso_end, priv->io_base + _REG(L_HSYNC_HE_ADDR)); 1743 writel_relaxed(0, priv->io_base + _REG(L_HSYNC_VS_ADDR)); 1744 writel_relaxed(max_lncnt, priv->io_base + _REG(L_HSYNC_VE_ADDR)); 1745 1746 /* Vsync signal */ 1747 writel_relaxed(vso_begin, priv->io_base + _REG(L_VSYNC_HS_ADDR)); 1748 writel_relaxed(vso_end, priv->io_base + _REG(L_VSYNC_HE_ADDR)); 1749 writel_relaxed(vso_bline, priv->io_base + _REG(L_VSYNC_VS_ADDR)); 1750 writel_relaxed(vso_eline, priv->io_base + _REG(L_VSYNC_VE_ADDR)); 1751 1752 writel_relaxed(0, priv->io_base + _REG(L_INV_CNT_ADDR)); 1754 priv->io_base + _REG(L_TCON_MISC_SEL_ADDR)); 1755 1756 priv->venc.current_mode = MESON_VENC_MODE_MIPI_DSI; 1757 } 1758 EXPORT_SYMBOL_GPL(meson_venc_mipi_dsi_mode_set); 1759 --- 0-DAY CI Kernel Test Service, Intel Corporation https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org