Hi Lars, I love your patch! Perhaps something to improve: [auto build test WARNING on linus/master] [also build test WARNING on next-20200608] [cannot apply to robh/for-next clk/clk-next pinctrl/devel v5.7] [if your patch is applied to the wrong git tree, please drop us a note to help improve the system. BTW, we also suggest to use '--base' option to specify the base tree in git format-patch, please see https://stackoverflow.com/a/37406982] url: https://github.com/0day-ci/linux/commits/Lars-Povlsen/Adding-support-for-... base: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git abfbb29297c27e3f101f348dc9e467b0fe70f919 config: nios2-allyesconfig (attached as .config) compiler: nios2-linux-gcc (GCC) 9.3.0 reproduce (this is a W=1 build): wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross chmod +x ~/bin/make.cross # save the attached .config to linux build tree COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-9.3.0 make.cross ARCH=nios2 If you fix the issue, kindly add following tag as appropriate Reported-by: kernel test robot <lkp(a)intel.com&gt; All warnings (new ones prefixed by >>, old ones prefixed by <<): drivers/pinctrl/pinctrl-ocelot.c: In function 'ocelot_hw_get_value': 659 | u32 value; | ^~~~~ drivers/pinctrl/pinctrl-ocelot.c: At top level: 785 | noinline int ocelot_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, | ^~~~~~~~~~~~~~~~~~ vim +/value +659 drivers/pinctrl/pinctrl-ocelot.c 649 650 static int ocelot_hw_get_value(struct ocelot_pinctrl *info, 651 unsigned int pin, 652 unsigned int reg, 653 int *val) 654 { 655 int ret = -ENOTSUPP; 656 657 if (info->pincfg) { 658 u32 regcfg = readl(info->pincfg + (pin * sizeof(u32))); 660 661 ret = 0; 662 switch (reg) { 663 case PINCONF_BIAS: 664 value = regcfg & BIAS_BITS; 665 break; 666 667 case PINCONF_SCHMITT: 668 value = regcfg & SCHMITT_BIT; 669 break; 670 671 case PINCONF_DRIVE_STRENGTH: 672 value = regcfg & DRIVE_BITS; 673 break; 674 675 default: 676 ret = -ENOTSUPP; 677 break; 678 } 679 } 680 return ret; 681 } 682 683 static int ocelot_hw_set_value(struct ocelot_pinctrl *info, 684 unsigned int pin, 685 unsigned int reg, 686 int val) 687 { 688 int ret = -ENOTSUPP; 689 690 if (info->pincfg) { 691 void __iomem *regaddr = info->pincfg + (pin * sizeof(u32)); 692 693 ret = 0; 694 switch (reg) { 695 case PINCONF_BIAS: 696 ocelot_clrsetbits(regaddr, BIAS_BITS, val); 697 break; 698 699 case PINCONF_SCHMITT: 700 ocelot_clrsetbits(regaddr, SCHMITT_BIT, val); 701 break; 702 703 case PINCONF_DRIVE_STRENGTH: 704 if (val <= 3) 705 ocelot_clrsetbits(regaddr, DRIVE_BITS, val); 706 else 707 ret = -EINVAL; 708 break; 709 710 default: 711 ret = -ENOTSUPP; 712 break; 713 } 714 } 715 return ret; 716 } 717 718 static int ocelot_pinconf_get(struct pinctrl_dev *pctldev, 719 unsigned int pin, unsigned long *config) 720 { 721 struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 722 u32 param = pinconf_to_config_param(*config); 723 int val, err; 724 725 switch (param) { 726 case PIN_CONFIG_BIAS_DISABLE: 727 case PIN_CONFIG_BIAS_PULL_UP: 728 case PIN_CONFIG_BIAS_PULL_DOWN: 729 err = ocelot_hw_get_value(info, pin, PINCONF_BIAS, &val); 730 if (err) 731 return err; 732 if (param == PIN_CONFIG_BIAS_DISABLE) 733 val = (val == 0 ? true : false); 734 else if (param == PIN_CONFIG_BIAS_PULL_DOWN) 735 val = (val & BIAS_PD_BIT ? true : false); 736 else /* PIN_CONFIG_BIAS_PULL_UP */ 737 val = (val & BIAS_PU_BIT ? true : false); 738 break; 739 740 case PIN_CONFIG_INPUT_SCHMITT_ENABLE: 741 err = ocelot_hw_get_value(info, pin, PINCONF_SCHMITT, &val); 742 if (err) 743 return err; 744 745 val = (val & SCHMITT_BIT ? true : false); 746 break; 747 748 case PIN_CONFIG_DRIVE_STRENGTH: 749 err = ocelot_hw_get_value(info, pin, PINCONF_DRIVE_STRENGTH, 750 &val); 751 if (err) 752 return err; 753 break; 754 755 case PIN_CONFIG_OUTPUT: 756 err = regmap_read(info->map, REG(OCELOT_GPIO_OUT, info, pin), 757 &val); 758 if (err) 759 return err; 760 val = !!(val & BIT(pin % 32)); 761 break; 762 763 case PIN_CONFIG_INPUT_ENABLE: 764 case PIN_CONFIG_OUTPUT_ENABLE: 765 err = regmap_read(info->map, REG(OCELOT_GPIO_OE, info, pin), 766 &val); 767 if (err) 768 return err; 769 val = val & BIT(pin % 32); 770 if (param == PIN_CONFIG_OUTPUT_ENABLE) 771 val = !!val; 772 else 773 val = !val; 774 break; 775 776 default: 777 return -ENOTSUPP; 778 } 779 780 *config = pinconf_to_config_packed(param, val); 781 782 return 0; 783 } 784 786 unsigned long *configs, unsigned int num_configs) 787 { 788 struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 789 u32 param, arg, p; 790 int cfg, err = 0; 791 792 for (cfg = 0; cfg < num_configs; cfg++) { 793 param = pinconf_to_config_param(configs[cfg]); 794 arg = pinconf_to_config_argument(configs[cfg]); 795 796 switch (param) { 797 case PIN_CONFIG_BIAS_DISABLE: 798 case PIN_CONFIG_BIAS_PULL_UP: 799 case PIN_CONFIG_BIAS_PULL_DOWN: 800 arg = (param == PIN_CONFIG_BIAS_DISABLE) ? 0 : 801 (param == PIN_CONFIG_BIAS_PULL_UP) ? BIAS_PU_BIT : 802 BIAS_PD_BIT; 803 804 err = ocelot_hw_set_value(info, pin, PINCONF_BIAS, arg); 805 if (err) 806 goto err; 807 808 break; 809 810 case PIN_CONFIG_INPUT_SCHMITT_ENABLE: 811 arg = arg ? SCHMITT_BIT : 0; 812 err = ocelot_hw_set_value(info, pin, PINCONF_SCHMITT, 813 arg); 814 if (err) 815 goto err; 816 817 break; 818 819 case PIN_CONFIG_DRIVE_STRENGTH: 820 err = ocelot_hw_set_value(info, pin, 821 PINCONF_DRIVE_STRENGTH, 822 arg); 823 if (err) 824 goto err; 825 826 break; 827 828 case PIN_CONFIG_OUTPUT_ENABLE: 829 case PIN_CONFIG_INPUT_ENABLE: 830 case PIN_CONFIG_OUTPUT: 831 p = pin % 32; 832 if (arg) 833 regmap_write(info->map, 834 REG(OCELOT_GPIO_OUT_SET, info, 835 pin), 836 BIT(p)); 837 else 838 regmap_write(info->map, 839 REG(OCELOT_GPIO_OUT_CLR, info, 840 pin), 841 BIT(p)); 842 regmap_update_bits(info->map, 843 REG(OCELOT_GPIO_OE, info, pin), 844 BIT(p), 845 param == PIN_CONFIG_INPUT_ENABLE ? 846 0 : BIT(p)); 847 break; 848 849 default: 850 err = -ENOTSUPP; 851 } 852 } 853 err: 854 return err; 855 } 856 --- 0-DAY CI Kernel Test Service, Intel Corporation https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org