Hi Edward, I love your patch! Perhaps something to improve: [auto build test WARNING on net-next/master] url: https://github.com/0day-ci/linux/commits/Edward-Cree/sfc_ef100-driver-for... base: https://git.kernel.org/pub/scm/linux/kernel/git/davem/net-next.git 8c8278a5b1a81e099ba883d8a0f9e3df9bdb1a74 config: i386-randconfig-s002-20200702 (attached as .config) compiler: gcc-9 (Debian 9.3.0-14) 9.3.0 reproduce: # apt-get install sparse # sparse version: v0.6.2-3-gfa153962-dirty # save the attached .config to linux build tree make W=1 C=1 CF='-fdiagnostic-prefix -D__CHECK_ENDIAN__' ARCH=i386 If you fix the issue, kindly add following tag as appropriate Reported-by: kernel test robot <lkp(a)intel.com&gt; All warnings (new ones prefixed by >>): In file included from include/linux/skbuff.h:31, from include/linux/if_ether.h:19, from include/uapi/linux/ethtool.h:19, from include/linux/ethtool.h:18, from include/linux/netdevice.h:37, from drivers/net/ethernet/sfc/net_driver.h:13, from drivers/net/ethernet/sfc/ef100.c:12: drivers/net/ethernet/sfc/ef100.c: In function 'ef100_pci_parse_continue_entry': 139 | #define DMA_BIT_MASK(n) (((n) == 64) ? ~0ULL : ((1ULL<<(n))-1)) | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 144 | DMA_BIT_MASK(ESF_GZ_TX_SEND_ADDR_WIDTH), | ^~~~~~~~~~~~ 139 | #define DMA_BIT_MASK(n) (((n) == 64) ? ~0ULL : ((1ULL<<(n))-1)) | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ drivers/net/ethernet/sfc/ef100.c:162:6: note: in expansion of macro 'DMA_BIT_MASK' 162 | DMA_BIT_MASK(ESF_GZ_TX_SEND_ADDR_WIDTH), | ^~~~~~~~~~~~ drivers/net/ethernet/sfc/ef100.c: In function 'ef100_pci_parse_xilinx_cap': 139 | #define DMA_BIT_MASK(n) (((n) == 64) ? ~0ULL : ((1ULL<<(n))-1)) | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ drivers/net/ethernet/sfc/ef100.c:339:5: note: in expansion of macro 'DMA_BIT_MASK' 339 | DMA_BIT_MASK(ESF_GZ_TX_SEND_ADDR_WIDTH), | ^~~~~~~~~~~~ drivers/net/ethernet/sfc/ef100.c: In function 'ef100_pci_probe': 139 | #define DMA_BIT_MASK(n) (((n) == 64) ? ~0ULL : ((1ULL<<(n))-1)) | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ drivers/net/ethernet/sfc/ef100.c:503:5: note: in expansion of macro 'DMA_BIT_MASK' 503 | DMA_BIT_MASK(ESF_GZ_TX_SEND_ADDR_WIDTH), | ^~~~~~~~~~~~ -- 45 | netdev_tx_t ef100_hard_start_xmit(struct sk_buff *skb, | ^~~~~~~~~~~~~~~~~~~~~ -- 15 | void __efx_rx_packet(struct efx_channel *channel) | ^~~~~~~~~~~~~~~ -- 16 | int efx_enqueue_skb_tso(struct efx_tx_queue *tx_queue, struct sk_buff *skb, | ^~~~~~~~~~~~~~~~~~~ sparse warnings: (new ones prefixed by >>) Please review and possibly fold the followup patch. vim +/DMA_BIT_MASK +144 drivers/net/ethernet/sfc/ef100.c 13 #include <linux/module.h> 14 #include <linux/aer.h> 15 #include "efx_common.h" 16 #include "efx_channels.h" 17 #include "io.h" 18 #include "ef100_nic.h" 19 #include "ef100_netdev.h" 20 #include "ef100_regs.h" 21 22 #define EFX_EF100_PCI_DEFAULT_BAR 2 23 24 /* Number of bytes at start of vendor specified extended capability that indicate 25 * that the capability is vendor specified. i.e. offset from value returned by 26 * pci_find_next_ext_capability() to beginning of vendor specified capability 27 * header. 28 */ 29 #define PCI_EXT_CAP_HDR_LENGTH 4 30 31 /* Expected size of a Xilinx continuation address table entry. */ 32 #define ESE_GZ_CFGBAR_CONT_CAP_MIN_LENGTH 16 33 34 struct ef100_func_ctl_window { 35 bool valid; 36 unsigned int bar; 37 u64 offset; 38 }; 39 40 static int ef100_pci_walk_xilinx_table(struct efx_nic *efx, u64 offset, 41 struct ef100_func_ctl_window *result); 42 43 /* Number of bytes to offset when reading bit position x with dword accessors. */ 44 #define ROUND_DOWN_TO_DWORD(x) (((x) & (~31)) >> 3) 45 46 #define EXTRACT_BITS(x, lbn, width) \ 47 ((x) >> ((lbn) & 31)) & ((1ull << (width)) - 1) 48 49 static u32 _ef100_pci_get_bar_bits_with_width(struct efx_nic *efx, 50 int structure_start, 51 int lbn, int width) 52 { 53 efx_dword_t dword; 54 55 efx_readd(efx, &dword, structure_start + ROUND_DOWN_TO_DWORD(lbn)); 56 57 return EXTRACT_BITS(le32_to_cpu(dword.u32[0]), lbn, width); 58 } 59 60 #define ef100_pci_get_bar_bits(efx, entry_location, bitdef) \ 61 _ef100_pci_get_bar_bits_with_width(efx, entry_location, \ 62 bitdef ## _LBN, bitdef ## _WIDTH) 63 64 static int ef100_pci_parse_ef100_entry(struct efx_nic *efx, int entry_location, 65 struct ef100_func_ctl_window *result) 66 { 67 u32 bar = ef100_pci_get_bar_bits(efx, entry_location, 68 ESF_GZ_CFGBAR_EF100_BAR); 69 u64 offset = ef100_pci_get_bar_bits(efx, entry_location, 70 ESF_GZ_CFGBAR_EF100_FUNC_CTL_WIN_OFF) << ESE_GZ_EF100_FUNC_CTL_WIN_OFF_SHIFT; 71 72 netif_dbg(efx, probe, efx->net_dev, 73 "Found EF100 function control window bar=%d offset=0x%llx\n", 74 bar, offset); 75 76 if (result->valid) { 77 netif_err(efx, probe, efx->net_dev, 78 "Duplicated EF100 table entry.\n"); 79 return -EINVAL; 80 } 81 82 if ((bar == ESE_GZ_CFGBAR_EF100_BAR_NUM_EXPANSION_ROM) || 83 (bar == ESE_GZ_CFGBAR_EF100_BAR_NUM_INVALID)) { 84 netif_err(efx, probe, efx->net_dev, 85 "Bad BAR value of %d in Xilinx capabilities EF100 entry.\n", 86 bar); 87 return -EINVAL; 88 } 89 90 result->bar = bar; 91 result->offset = offset; 92 result->valid = true; 93 return 0; 94 } 95 96 static bool ef100_pci_does_bar_overflow(struct efx_nic *efx, int bar, 97 u64 next_entry) 98 { 99 return next_entry + ESE_GZ_CFGBAR_ENTRY_HEADER_SIZE > 100 pci_resource_len(efx->pci_dev, bar); 101 } 102 103 /* Parse a Xilinx capabilities table entry describing a continuation to a new 104 * sub-table. 105 */ 106 static int ef100_pci_parse_continue_entry(struct efx_nic *efx, int entry_location, 107 struct ef100_func_ctl_window *result) 108 { 109 unsigned int previous_bar; 110 efx_oword_t entry; 111 u64 offset; 112 int rc = 0; 113 u32 bar; 114 115 efx_reado(efx, &entry, entry_location); 116 117 bar = EFX_OWORD_FIELD32(entry, ESF_GZ_CFGBAR_CONT_CAP_BAR); 118 119 offset = EFX_OWORD_FIELD64(entry, ESF_GZ_CFGBAR_CONT_CAP_OFFSET) << 120 ESE_GZ_CONT_CAP_OFFSET_BYTES_SHIFT; 121 122 previous_bar = efx->mem_bar; 123 124 if ((bar == ESE_GZ_VSEC_BAR_NUM_EXPANSION_ROM) || 125 (bar == ESE_GZ_VSEC_BAR_NUM_INVALID)) { 126 netif_err(efx, probe, efx->net_dev, 127 "Bad BAR value of %d in Xilinx capabilities sub-table.\n", 128 bar); 129 return -EINVAL; 130 } 131 132 if (bar != previous_bar) { 133 efx_fini_io(efx); 134 135 if (ef100_pci_does_bar_overflow(efx, bar, offset)) { 136 netif_err(efx, probe, efx->net_dev, 137 "Xilinx table will overrun BAR[%d] offset=0x%llx\n", 138 bar, offset); 139 return -EINVAL; 140 } 141 142 /* Temporarily map new BAR. */ 143 rc = efx_init_io(efx, bar, 145 pci_resource_len(efx->pci_dev, bar)); 146 if (rc) { 147 netif_err(efx, probe, efx->net_dev, 148 "Mapping new BAR for Xilinx table failed, rc=%d\n", rc); 149 return rc; 150 } 151 } 152 153 rc = ef100_pci_walk_xilinx_table(efx, offset, result); 154 if (rc) 155 return rc; 156 157 if (bar != previous_bar) { 158 efx_fini_io(efx); 159 160 /* Put old BAR back. */ 161 rc = efx_init_io(efx, previous_bar, 162 DMA_BIT_MASK(ESF_GZ_TX_SEND_ADDR_WIDTH), 163 pci_resource_len(efx->pci_dev, previous_bar)); 164 if (rc) { 165 netif_err(efx, probe, efx->net_dev, 166 "Putting old BAR back failed, rc=%d\n", rc); 167 return rc; 168 } 169 } 170 171 return 0; 172 } 173 --- 0-DAY CI Kernel Test Service, Intel Corporation https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org