There are fringe cases that are more complex, and maybe the correct reading
of the spec is to setup routing to avoid optimal paths, but it certainly is
possible to configure switches in a way that could not guarentee global
If someone configures a multipath PCIe topology I think they will have potential for out
of order RDMA reads/writes regardless of whether the target MR is in system memory of PCIe
memory. So I don't think these crazy topologies are uniquely problematic for IOPMEM.