Re: [PATCH v2 5/9] x86, pmem: push fallback handling to arch code

On Wed, 2015-08-26 at 14:41 +0200, Christoph Hellwig wrote: > I like the intent behind this, but not the implementation. > > I think the right approach is to keep the defaults in linux/pmem.h > and simply not set CONFIG_ARCH_HAS_PMEM_API for x86-32. Yes, that makes things much cleaner. Revised patch and changelog below: 8<---- Subject: x86, pmem: clarify that ARCH_HAS_PMEM_API implies PMEM mapped WB From: Dan Williams <dan.j.williams(a)intel.com&gt; Given that a write-back (WB) mapping plus non-temporal stores is expected to be the most efficient way to access PMEM, update the definition of ARCH_HAS_PMEM_API to imply arch support for WB-mapped-PMEM. This is needed as a pre-requisite for adding PMEM to the direct map and mapping it with struct page. The above clarification for X86_64 means that memcpy_to_pmem() is permitted to use the non-temporal arch_memcpy_to_pmem() rather than needlessly fall back to default_memcpy_to_pmem() when the pcommit instruction is not available. When arch_memcpy_to_pmem() is not guaranteed to flush writes out of cache, i.e. on older X86_32 implementations where non-temporal stores may just dirty cache, ARCH_HAS_PMEM_API is simply disabled. The default fall back for persistent memory handling remains. Namely, map it with the WT (write-through) cache-type and hope for the best. arch_has_pmem_api() is updated to only indicate whether the arch provides the proper helpers to meet the minimum "writes are visible outside the cache hierarchy after memcpy_to_pmem() + wmb_pmem()". Code that cares whether wmb_pmem() actually flushes writes to pmem must now call arch_has_wmb_pmem() directly. Cc: Thomas Gleixner <tglx(a)linutronix.de&gt; Cc: Ingo Molnar <mingo(a)redhat.com&gt; Cc: "H. Peter Anvin" <hpa(a)zytor.com&gt; Cc: Toshi Kani <toshi.kani(a)hp.com&gt; Cc: Ross Zwisler <ross.zwisler(a)linux.intel.com&gt; Cc: Christoph Hellwig <hch(a)lst.de&gt; [hch: set ARCH_HAS_PMEM_API=n on X86_32] Signed-off-by: Dan Williams <dan.j.williams(a)intel.com&gt;