On Thu, Dec 29, 2016 at 10:23:15AM -0800, Dan Williams wrote:
> BTW, your "it's iovec, only non-temporal stores
there" logics in
> arch_copy_from_iter_pmem() is simply wrong - for one thing, unaligned
> copies will have parts done via normal stores, for another 32bit will
> _not_ go for non-caching codepath for short copies. What semantics do
> we really need there?
For typical pmem platforms we need to make sure all the writes are on
the way to memory such than a later sfence can guarantee that all
previous writes are visible to the platform "ADR" logic. ADR handles
flushing memory controller write buffers to media. At a minimum
arch_copy_from_iter_pmem() needs to trigger a clwb (unordered cache
line writeback) of each touched cache line if it is not using a cache
Um... Then we do have a problem - nocache variant of uaccess primitives
does *not* guarantee that clwb is redundant.
What about the requirements of e.g. tcp_sendmsg() with its use of
skb_add_data_nocache()? What warranties do we need there?