On Tue, Nov 12, 2019 at 09:15:18AM -0800, Dan Williams wrote: > On Mon, Nov 11, 2019 at 6:12 PM Bharat Kumar Gogada <bharatku(a)xilinx.com&gt; wrote: > > > > Hi All, > > > > As per Documentation/filesystems/dax.txt > > > > The DAX code does not work correctly on architectures which have > > virtually mapped caches such as ARM, MIPS and SPARC. > > > > Can anyone please shed light on dax filesystem issue w.r.t ARM architecture ? > > The concern is VIVT caches since the kernel will want to flush pmem > addresses with different virtual addresses than what userspace is > using. As far as I know, ARMv8 has VIPT caches, so should not have an > issue. Willy initially wrote those restrictions, but I am assuming > that the concern was managing the caches in the presence of virtual > aliases. The kernel will also access data at different virtual addresses from userspace. So VIVT CPUs will be mmap/read/write incoherent, as well as being flush incoherent.