On Tue, 2 Jul 2019 at 06:44, Thomas Gleixner <tglx(a)linutronix.de&gt; wrote: > > While that CPU0 hotplug test case is surely an esoteric issue, the APIC > emulation is still wrong, Even if the play_dead() code would not enable > interrupts then the pending IRR bit would turn into an ISR .. interrupt > when the APIC is reenabled on startup. >From SDM 10.4.7.2 Local APIC State After It Has Been Software Disabled * Pending interrupts in the IRR and ISR registers are held and require masking or handling by the CPU.

In your testing, hardware cpu will not respect soft disable APIC when IRR has already been set or APICv posted-interrupt is in flight, so we can skip soft disable APIC checking when clearing IRR and set ISR, continue to respect soft disable APIC when attempting to set IRR. Could you try below fix?

diff --git a/arch/x86/kvm/lapic.c b/arch/x86/kvm/lapic.c index 05d8934..f857a12 100644 --- a/arch/x86/kvm/lapic.c +++ b/arch/x86/kvm/lapic.c @@ -2376,7 +2376,7 @@ int kvm_apic_has_interrupt(struct kvm_vcpu *vcpu) struct kvm_lapic *apic = vcpu->arch.apic; u32 ppr; - if (!apic_enabled(apic)) + if (!kvm_apic_hw_enabled(apic)) return -1; __apic_update_ppr(apic, &ppr);