Your AFU almost certainly ignored c1TxAlmFull and overran the ingress c1Tx FIFO. Up to CCI_TX_ALMOST_FULL_THRESHOLD flits may be sent after c1TxAlmFull is asserted. Note that each individual line in a multi-line write counts toward the limit. The other less likely possibility is that reset isn’t wired properly to the cci_mpf() wrapper module. The FIFO primitive raises this error in simulation. On HW, the cci_mpf_prim_fifo_lutram() stops all traffic by forcing the FIFO to appear empty once an overrun is detected. It does this because a deadlock is easier to debug than a dropped packet. If follow-up is needed, you could use https://github.com/OPAE/intel-fpga-bbb/issues instead of this mailing list. -Michael From: OPAE <opae-bounces(a)lists.01.org&gt; on behalf of Abel Eneyew <mul.abel43(a)gmail.com&gt; Date: Saturday, July 6, 2019 at 3:43 PM To: &quot;opae(a)lists.01.org&quot; <opae(a)lists.01.org&gt; Subject: [OPAE] Intel BBB MPF fifo alm full signals Is there any signals that allows me to know if the MPF fifo is full or not? I am stuck at an error like this The fifo in question can be found here https://github.com/OPAE/intel-fpga-bbb/blob/master/BBB_cci_mpf/hw/rtl/cci... as can be seen in the code it can only enque 2 elements.