Your AFU almost certainly ignored c1TxAlmFull and overran the ingress c1Tx FIFO. Up to
CCI_TX_ALMOST_FULL_THRESHOLD flits may be sent after c1TxAlmFull is asserted. Note that
each individual line in a multi-line write counts toward the limit. The other less likely
possibility is that reset isn’t wired properly to the cci_mpf() wrapper module.
The FIFO primitive raises this error in simulation. On HW, the cci_mpf_prim_fifo_lutram()
stops all traffic by forcing the FIFO to appear empty once an overrun is detected. It does
this because a deadlock is easier to debug than a dropped packet.
If follow-up is needed, you could use
https://github.com/OPAE/intel-fpga-bbb/issues
instead of this mailing list.
-Michael
From: OPAE <opae-bounces(a)lists.01.org> on behalf of Abel Eneyew
<mul.abel43(a)gmail.com>
Date: Saturday, July 6, 2019 at 3:43 PM
To: "opae(a)lists.01.org" <opae(a)lists.01.org>
Subject: [OPAE] Intel BBB MPF fifo alm full signals
Is there any signals that allows me to know if the MPF fifo is full or not? I am stuck at
an error like this
intel-fpga-bbb/BBB_cci_mpf/hw/sim/../rtl/cci-mpf-prims/cci_mpf_prim_fifo_lutram.sv<http://cci_mpf_prim_fifo_lutram.sv>",
252:
ase_top.platform_shim_ccip_std_afu.ccip_std_afu.mpf.mpf_pipe.mpf_edge_afu.req_b.ba.c1_fifo.fifo.ctrl.unnamed$$_0:
started at 2223785000ps failed at 2223785000ps
Offending 'notFull'
Fatal:
"intel-fpga-bbb/BBB_cci_mpf/hw/sim/../rtl/cci-mpf-prims/cci_mpf_prim_fifo_lutram.sv<http://cci_mpf_prim_fifo_lutram.sv>",
252:
ase_top.platform_shim_ccip_std_afu.ccip_std_afu.mpf.mpf_pipe.mpf_edge_afu.req_b.ba.c1_fifo.fifo.ctrl.unnamed$$_0:
at time 2223785000 ps
cci_mpf_prim_fifo_lutram: ENQ to full fifo
$finish called from file
"intel-fpga-bbb/BBB_cci_mpf/hw/sim/../rtl/cci-mpf-prims/cci_mpf_prim_fifo_lutram.sv<http://cci_mpf_prim_fifo_lutram.sv>",
line 252.
The fifo in question can be found here
https://github.com/OPAE/intel-fpga-bbb/blob/master/BBB_cci_mpf/hw/rtl/cci...
as can be seen in the code it can only enque 2 elements.