Because the MMIO address lines in the hardware don’t include the low 2 bits. The CCI-P spec. requires that they always be 0 since the minimum MMIO granularity is 4 bytes. The software and CPU do have those low 2 bits, so the CPU-side computation differs by a factor of 4. -Michael From: OPAE <opae-bounces(a)lists.01.org&gt; on behalf of Abel Eneyew <mul.abel43(a)gmail.com&gt; Date: Thursday, May 30, 2019 at 12:03 PM To: &quot;opae(a)lists.01.org&quot; <opae(a)lists.01.org&gt; Subject: [OPAE] Intel Fpga BBB Tutorial I am at the second part of the tutorial. But I am having difficulties understanding the mmio addressing part. Specificallly https://github.com/OPAE/intel-fpga-bbb/blob/master/samples/tutorial/02_pl... why do we multiply the address by 4 but in the hardware part https://github.com/OPAE/intel-fpga-bbb/blob/master/samples/tutorial/02_pl... it isn't multiplied. Why do we need to multiply it by 4 in the software part? Sorry if this is not an interesting question. But I am new and it is confusing. Regards Abel