Hi The likely explanation for this is that there may be a mismatch between the FSP binary and the UPD header file. Can you try the FSP binary/header files from the github and confirm the register values? Thanks Ravi -----Original Message----- From: Andrey V <avinok(a)gmail.com&gt; Sent: Wednesday, May 20, 2020 7:23 AM To: sbl-devel(a)lists.01.org Subject: [Sbl-devel] Set PCIe to -3.5db (LCTL2_LSTS2 bit 6) Hi I am configuring as recommended in https://github.com/slimbootloader/slimbootloader/issues/680 the LCTL2_LSTS2 bit 6. The code in SBL has a comment like: /* When the Link is operating at 5.0 GT/s speed, this bit selects the level of de-emphasis for an Upstream component. 1b:-3.5 dB 0b:-6 dB. 0:Disable, 1:Enable(Default). */ Therefore, adding the code in Stage2BoardInitLib.c like: // Gen2 and -3.5db FspsConfig->PcieRpSelectableDeemphasis[2] = 0x2; FspsConfig->PcieRpSelectableDeemphasis [3] = 0x2; FspsConfig->PcieRpSelectableDeemphasis[4] = 0x2; FspsConfig->PcieRpSelectableDeemphasis[5] = 0x2; I am expect the LCTL2_LSTS2 bit 6 is set. However, the BIOS log after boot: ------------------ PCIe Config ------------------ RootPort[2] SelectableDeemphasis = 0 RootPort[3] SelectableDeemphasis = 0 RootPort[4] SelectableDeemphasis = 0 RootPort[5] SelectableDeemphasis = 0 How, can I verify the settings of the LCTL2_LSTS2 bit 6 ? Andrey -- Sbl-devel mailing list -- sbl-devel(a)lists.01.org To unsubscribe send an email to sbl-devel-leave(a)lists.01.org

Would it be possible for you read the PCIe RP's configuration space? Other option for you is to use the header files for the debug FSP that you are using. Thanks. -----Original Message----- From: Andrey V <avinok(a)gmail.com&gt; Sent: Thursday, May 21, 2020 6:36 AM To: sbl-devel(a)lists.01.org Subject: [Sbl-devel] Re: Set PCIe to -3.5db (LCTL2_LSTS2 bit 6) with a SBL checkout to 1ac8e390c473ee648defa9dcd90294d8c825e6f9 and FSP MR6 not in debug I do not see any PCI setting printed How can I verify it ? -- Sbl-devel mailing list -- sbl-devel(a)lists.01.org To unsubscribe send an email to sbl-devel-leave(a)lists.01.org

Regarding the header files - I am referring to the files in https://github.com/intel/FSP/tree/master/ApolloLakeFspBinPkg/Include. The header files are FSP version dependent. So if you switch to a different FSP binary version, you need to make sure you have the correct version of the header files as well. Link Control2 / Link Status 2 are registers in the PCIe configuration space. Each PCIe RP has its own configuration space that you can read. If you are using the OsLoader payload, you can go to the Shell and use the "pci bus# dev# func#" to display the config space. Thanks. -----Original Message----- From: Andrey V <avinok(a)gmail.com&gt; Sent: Thursday, May 21, 2020 8:07 AM To: sbl-devel(a)lists.01.org Subject: [Sbl-devel] Re: Set PCIe to -3.5db (LCTL2_LSTS2 bit 6) "Would it be possible for you read the PCIe RP's configuration space? " can you tell me where it is ? What do you mean header files for the debug FSP ? I have FSP MR5 debug and the latest from SBL MR6 not debug Thanks -- Sbl-devel mailing list -- sbl-devel(a)lists.01.org To unsubscribe send an email to sbl-devel-leave(a)lists.01.org