Hello, Thanks for letting us know this issue. Unfortunately, I only have 2GB UP2 board, so I can just tell you to modify some memory configuration parameters as below. I hope this would help your issue. --- a/Platform/ApollolakeBoardPkg/CfgData/CfgData_Ext_Up2.dlt +++ b/Platform/ApollolakeBoardPkg/CfgData/CfgData_Ext_Up2.dlt @@ -20,20 +20,20 @@ PLATFORMID_CFG_DATA.PlatformId | 0x000E PLAT_NAME_CFG_DATA.PlatformName | 'UP2' -MEMORY_CFG_DATA.DualRankSupportEnable | 0x0 +MEMORY_CFG_DATA.DualRankSupportEnable | 0x1 MEMORY_CFG_DATA.RmtMode | 0x0 MEMORY_CFG_DATA.MemorySizeLimit | 0x0 MEMORY_CFG_DATA.Ch0_RankEnable | 0x1 MEMORY_CFG_DATA.Ch0_DramDensity | 0x2 MEMORY_CFG_DATA.Ch1_RankEnable | 0x1 MEMORY_CFG_DATA.Ch1_DramDensity | 0x2 -MEMORY_CFG_DATA.Ch2_RankEnable | 0x0 +MEMORY_CFG_DATA.Ch2_RankEnable | 0x1 MEMORY_CFG_DATA.Ch2_DramDensity | 0x2 -MEMORY_CFG_DATA.Ch3_RankEnable | 0x0 +MEMORY_CFG_DATA.Ch3_RankEnable | 0x1 MEMORY_CFG_DATA.Ch3_DramDensity | 0x2 MEMORY_CFG_DATA.RmtCheckRun | 0x3 Best Regards, Aiden -----Original Message----- From: Sbl-devel [mailto:sbl-devel-bounces@lists.01.org] On Behalf Of zhou_c(a)hoperun.com Sent: Tuesday, December 4, 2018 10:16 PM To: sbl-devel <sbl-devel(a)lists.01.org&gt; Cc: zhou_x1 <zhou_x1(a)hoperun.com&gt; Subject: [Sbl-devel] How to update Mem info in E820 Table Hi Guys, Recently, I got an issue on UP2 boards after deploying latest SBL on it. Linux kernel only got 2G memory. But there is 8G DDR physical memory on board. After checking dmesg:         [    0.000000] BIOS-e820: [mem 0x0000000000000000-0x000000000008ffff] usable         [    0.000000] BIOS-e820: [mem 0x0000000000090000-0x00000000000fffff] reserved         [    0.000000] BIOS-e820: [mem 0x0000000000100000-0x000000000fffffff] usable         [    0.000000] BIOS-e820: [mem 0x0000000010000000-0x0000000012150fff] reserved         [    0.000000] BIOS-e820: [mem 0x0000000012151000-0x000000006dffffff] usable         [    0.000000] BIOS-e820: [mem 0x0000000072800000-0x0000000079703fff] usable         [    0.000000] BIOS-e820: [mem 0x0000000079704000-0x000000007a003fff] reserved         [    0.000000] BIOS-e820: [mem 0x000000007a004000-0x000000007a06bfff] ACPI data         [    0.000000] BIOS-e820: [mem 0x000000007a06c000-0x000000007a073fff] ACPI NVS         [    0.000000] BIOS-e820: [mem 0x000000007a074000-0x000000007fffffff] reserved         [    0.000000] BIOS-e820: [mem 0x00000000ff800000-0x00000000ffffffff] reserved And SBL log shows the same case:         Call FspSiliconInit ...         Success         MEM: 0000000000000000 00000000000A0000 00 1         MEM: 00000000000A0000 0000000000060000 00 2         MEM: 0000000000100000 000000000FF00000 00 1         MEM: 0000000010000000 0000000002151000 00 2         MEM: 0000000012151000 00000000675B3000 00 1         MEM: 0000000079704000 0000000000900000 01 2         MEM: 000000007A004000 0000000000068000 00 3         MEM: 000000007A06C000 0000000000008000 00 4         MEM: 000000007A074000 0000000000B8C000 00 2         MEM: 000000007AC00000 0000000000400000 00 2         MEM: 000000007B000000 0000000000800000 00 2         MEM: 000000007B800000 0000000004800000 00 2         MEM: 00000000FF800000 0000000000800000 00 2         MP Init (Wakeup)         MP Init (Run) Actually, there is another DDR memory block (mem 0x0000000100000000-0x000000027fffffff) on the board. Could any one provide some methods to update the SBL Memory Info, please? -- Sbl-devel mailing list Sbl-devel(a)lists.01.org https://lists.01.org/mailman/listinfo/sbl-devel

Hi Jerry, Good to hear that you got increased size. Then, you can change all ChX_RankEnable 0x1 to 0x3. Looking forward to good news. --- a/Platform/ApollolakeBoardPkg/CfgData/CfgData_Ext_Up2.dlt +++ b/Platform/ApollolakeBoardPkg/CfgData/CfgData_Ext_Up2.dlt @@ -20,20 +20,20 @@ PLATFORMID_CFG_DATA.PlatformId | 0x000E PLAT_NAME_CFG_DATA.PlatformName | 'UP2' -MEMORY_CFG_DATA.DualRankSupportEnable | 0x0 +MEMORY_CFG_DATA.DualRankSupportEnable | 0x1 MEMORY_CFG_DATA.RmtMode | 0x0 MEMORY_CFG_DATA.MemorySizeLimit | 0x0 -MEMORY_CFG_DATA.Ch0_RankEnable | 0x1 +MEMORY_CFG_DATA.Ch0_RankEnable | 0x3 MEMORY_CFG_DATA.Ch0_DramDensity | 0x2 -MEMORY_CFG_DATA.Ch1_RankEnable | 0x1 +MEMORY_CFG_DATA.Ch1_RankEnable | 0x3 MEMORY_CFG_DATA.Ch1_DramDensity | 0x2 -MEMORY_CFG_DATA.Ch2_RankEnable | 0x0 +MEMORY_CFG_DATA.Ch2_RankEnable | 0x3 MEMORY_CFG_DATA.Ch2_DramDensity | 0x2 -MEMORY_CFG_DATA.Ch3_RankEnable | 0x0 +MEMORY_CFG_DATA.Ch3_RankEnable | 0x3 MEMORY_CFG_DATA.Ch3_DramDensity | 0x2 MEMORY_CFG_DATA.RmtCheckRun | 0x3 Best Regards, Aiden -----Original Message----- From: zhou_c(a)hoperun.com [mailto:zhou_c@hoperun.com] Sent: Wednesday, December 5, 2018 6:25 PM To: Park, Aiden <aiden.park(a)intel.com&gt;; sbl-devel <sbl-devel(a)lists.01.org&gt; Cc: zhou_x1 <zhou_x1(a)hoperun.com&gt; Subject: Re: RE: [Sbl-devel] How to update Mem info in E820 Table Hi Aiden, Thanks for your reply. My memory size increase to 4G from 2G after applying your patch. Could your provide some more help to us for detecting whole DDR memory [8G]? And what necessary information do you need? Thanks, Jerry Zhou   From: Park, Aiden Date: 2018-12-06 08:56 To: zhou_c@hoperun.com; sbl-devel CC: zhou_x1 Subject: RE: [Sbl-devel] How to update Mem info in E820 Table Hello,   Thanks for letting us know this issue. Unfortunately, I only have 2GB UP2 board, so I can just tell you to modify some memory configuration parameters as below. I hope this would help your issue.   --- a/Platform/ApollolakeBoardPkg/CfgData/CfgData_Ext_Up2.dlt +++ b/Platform/ApollolakeBoardPkg/CfgData/CfgData_Ext_Up2.dlt @@ -20,20 +20,20 @@ PLATFORMID_CFG_DATA.PlatformId           | 0x000E   PLAT_NAME_CFG_DATA.PlatformName          | 'UP2' -MEMORY_CFG_DATA.DualRankSupportEnable    | 0x0 +MEMORY_CFG_DATA.DualRankSupportEnable    | 0x1 MEMORY_CFG_DATA.RmtMode                  | 0x0 MEMORY_CFG_DATA.MemorySizeLimit          | 0x0 MEMORY_CFG_DATA.Ch0_RankEnable           | 0x1 MEMORY_CFG_DATA.Ch0_DramDensity          | 0x2 MEMORY_CFG_DATA.Ch1_RankEnable           | 0x1 MEMORY_CFG_DATA.Ch1_DramDensity          | 0x2 -MEMORY_CFG_DATA.Ch2_RankEnable           | 0x0 +MEMORY_CFG_DATA.Ch2_RankEnable           | 0x1 MEMORY_CFG_DATA.Ch2_DramDensity          | 0x2 -MEMORY_CFG_DATA.Ch3_RankEnable           | 0x0 +MEMORY_CFG_DATA.Ch3_RankEnable           | 0x1 MEMORY_CFG_DATA.Ch3_DramDensity          | 0x2 MEMORY_CFG_DATA.RmtCheckRun              | 0x3   Best Regards, Aiden   -----Original Message----- From: Sbl-devel [mailto:sbl-devel-bounces@lists.01.org] On Behalf Of zhou_c(a)hoperun.com Sent: Tuesday, December 4, 2018 10:16 PM To: sbl-devel <sbl-devel(a)lists.01.org&gt; Cc: zhou_x1 <zhou_x1(a)hoperun.com&gt; Subject: [Sbl-devel] How to update Mem info in E820 Table   Hi Guys,   Recently, I got an issue on UP2 boards after deploying latest SBL on it. Linux kernel only got 2G memory. But there is 8G DDR physical memory on board.   After checking dmesg:           [    0.000000] BIOS-e820: [mem 0x0000000000000000-0x000000000008ffff] usable         [    0.000000] BIOS-e820: [mem 0x0000000000090000-0x00000000000fffff] reserved         [    0.000000] BIOS-e820: [mem 0x0000000000100000-0x000000000fffffff] usable         [    0.000000] BIOS-e820: [mem 0x0000000010000000-0x0000000012150fff] reserved         [    0.000000] BIOS-e820: [mem 0x0000000012151000-0x000000006dffffff] usable         [    0.000000] BIOS-e820: [mem 0x0000000072800000-0x0000000079703fff] usable         [    0.000000] BIOS-e820: [mem 0x0000000079704000-0x000000007a003fff] reserved         [    0.000000] BIOS-e820: [mem 0x000000007a004000-0x000000007a06bfff] ACPI data         [    0.000000] BIOS-e820: [mem 0x000000007a06c000-0x000000007a073fff] ACPI NVS         [    0.000000] BIOS-e820: [mem 0x000000007a074000-0x000000007fffffff] reserved         [    0.000000] BIOS-e820: [mem 0x00000000ff800000-0x00000000ffffffff] reserved   And SBL log shows the same case:           Call FspSiliconInit ...         Success         MEM: 0000000000000000 00000000000A0000 00 1         MEM: 00000000000A0000 0000000000060000 00 2         MEM: 0000000000100000 000000000FF00000 00 1         MEM: 0000000010000000 0000000002151000 00 2         MEM: 0000000012151000 00000000675B3000 00 1         MEM: 0000000079704000 0000000000900000 01 2         MEM: 000000007A004000 0000000000068000 00 3         MEM: 000000007A06C000 0000000000008000 00 4         MEM: 000000007A074000 0000000000B8C000 00 2         MEM: 000000007AC00000 0000000000400000 00 2         MEM: 000000007B000000 0000000000800000 00 2         MEM: 000000007B800000 0000000004800000 00 2         MEM: 00000000FF800000 0000000000800000 00 2         MP Init (Wakeup)         MP Init (Run)   Actually, there is another DDR memory block (mem 0x0000000100000000-0x000000027fffffff) on the board. Could any one provide some methods to update the SBL Memory Info, please?   -- Sbl-devel mailing list Sbl-devel(a)lists.01.org https://lists.01.org/mailman/listinfo/sbl-devel

Hi Jerry, You are very welcome. And, please feel free to open an issue in github <https://github.com/slimbootloader/slimbootloader/issues> as well. Best Regards, Aiden -----Original Message----- From: zhou_c(a)hoperun.com [mailto:zhou_c@hoperun.com] Sent: Wednesday, December 5, 2018 7:32 PM To: Park, Aiden <aiden.park(a)intel.com&gt;; sbl-devel <sbl-devel(a)lists.01.org&gt; Cc: zhou_x1 <zhou_x1(a)hoperun.com&gt; Subject: Re: RE: [Sbl-devel] How to update Mem info in E820 Table Hi Aiden, Great! This modification is really good for me! Thanks for your help! Thanks, Jerry Zhou -----Original Message----- From: Park, Aiden Date: 2018-12-06 11:15 To: zhou_c@hoperun.com; sbl-devel CC: zhou_x1 Subject: RE: RE: [Sbl-devel] How to update Mem info in E820 Table Hi Jerry,   Good to hear that you got increased size. Then, you can change all ChX_RankEnable 0x1 to 0x3. Looking forward to good news.   --- a/Platform/ApollolakeBoardPkg/CfgData/CfgData_Ext_Up2.dlt +++ b/Platform/ApollolakeBoardPkg/CfgData/CfgData_Ext_Up2.dlt @@ -20,20 +20,20 @@ PLATFORMID_CFG_DATA.PlatformId           | 0x000E   PLAT_NAME_CFG_DATA.PlatformName          | 'UP2' -MEMORY_CFG_DATA.DualRankSupportEnable    | 0x0 +MEMORY_CFG_DATA.DualRankSupportEnable    | 0x1 MEMORY_CFG_DATA.RmtMode                  | 0x0 MEMORY_CFG_DATA.MemorySizeLimit          | 0x0 -MEMORY_CFG_DATA.Ch0_RankEnable           | 0x1 +MEMORY_CFG_DATA.Ch0_RankEnable           | 0x3 MEMORY_CFG_DATA.Ch0_DramDensity          | 0x2 -MEMORY_CFG_DATA.Ch1_RankEnable           | 0x1 +MEMORY_CFG_DATA.Ch1_RankEnable           | 0x3 MEMORY_CFG_DATA.Ch1_DramDensity          | 0x2 -MEMORY_CFG_DATA.Ch2_RankEnable           | 0x0 +MEMORY_CFG_DATA.Ch2_RankEnable           | 0x3 MEMORY_CFG_DATA.Ch2_DramDensity          | 0x2 -MEMORY_CFG_DATA.Ch3_RankEnable           | 0x0 +MEMORY_CFG_DATA.Ch3_RankEnable           | 0x3 MEMORY_CFG_DATA.Ch3_DramDensity          | 0x2 MEMORY_CFG_DATA.RmtCheckRun              | 0x3   Best Regards, Aiden   -----Original Message----- From: zhou_c(a)hoperun.com [mailto:zhou_c@hoperun.com] Sent: Wednesday, December 5, 2018 6:25 PM To: Park, Aiden <aiden.park(a)intel.com&gt;; sbl-devel <sbl-devel(a)lists.01.org&gt; Cc: zhou_x1 <zhou_x1(a)hoperun.com&gt; Subject: Re: RE: [Sbl-devel] How to update Mem info in E820 Table   Hi Aiden,   Thanks for your reply. My memory size increase to 4G from 2G after applying your patch. Could your provide some more help to us for detecting whole DDR memory [8G]? And what necessary information do you need?   Thanks, Jerry Zhou   From: Park, Aiden Date: 2018-12-06 08:56 To: zhou_c@hoperun.com; sbl-devel CC: zhou_x1 Subject: RE: [Sbl-devel] How to update Mem info in E820 Table Hello,   Thanks for letting us know this issue. Unfortunately, I only have 2GB UP2 board, so I can just tell you to modify some memory configuration parameters as below. I hope this would help your issue.   --- a/Platform/ApollolakeBoardPkg/CfgData/CfgData_Ext_Up2.dlt +++ b/Platform/ApollolakeBoardPkg/CfgData/CfgData_Ext_Up2.dlt @@ -20,20 +20,20 @@ PLATFORMID_CFG_DATA.PlatformId           | 0x000E   PLAT_NAME_CFG_DATA.PlatformName          | 'UP2' -MEMORY_CFG_DATA.DualRankSupportEnable    | 0x0 +MEMORY_CFG_DATA.DualRankSupportEnable    | 0x1 MEMORY_CFG_DATA.RmtMode                  | 0x0 MEMORY_CFG_DATA.MemorySizeLimit          | 0x0 MEMORY_CFG_DATA.Ch0_RankEnable           | 0x1 MEMORY_CFG_DATA.Ch0_DramDensity          | 0x2 MEMORY_CFG_DATA.Ch1_RankEnable           | 0x1 MEMORY_CFG_DATA.Ch1_DramDensity          | 0x2 -MEMORY_CFG_DATA.Ch2_RankEnable           | 0x0 +MEMORY_CFG_DATA.Ch2_RankEnable           | 0x1 MEMORY_CFG_DATA.Ch2_DramDensity          | 0x2 -MEMORY_CFG_DATA.Ch3_RankEnable           | 0x0 +MEMORY_CFG_DATA.Ch3_RankEnable           | 0x1 MEMORY_CFG_DATA.Ch3_DramDensity          | 0x2 MEMORY_CFG_DATA.RmtCheckRun              | 0x3   Best Regards, Aiden   -----Original Message----- From: Sbl-devel [mailto:sbl-devel-bounces@lists.01.org] On Behalf Of zhou_c(a)hoperun.com Sent: Tuesday, December 4, 2018 10:16 PM To: sbl-devel <sbl-devel(a)lists.01.org&gt; Cc: zhou_x1 <zhou_x1(a)hoperun.com&gt; Subject: [Sbl-devel] How to update Mem info in E820 Table   Hi Guys,   Recently, I got an issue on UP2 boards after deploying latest SBL on it. Linux kernel only got 2G memory. But there is 8G DDR physical memory on board.   After checking dmesg:           [    0.000000] BIOS-e820: [mem 0x0000000000000000-0x000000000008ffff] usable         [    0.000000] BIOS-e820: [mem 0x0000000000090000-0x00000000000fffff] reserved         [    0.000000] BIOS-e820: [mem 0x0000000000100000-0x000000000fffffff] usable         [    0.000000] BIOS-e820: [mem 0x0000000010000000-0x0000000012150fff] reserved         [    0.000000] BIOS-e820: [mem 0x0000000012151000-0x000000006dffffff] usable         [    0.000000] BIOS-e820: [mem 0x0000000072800000-0x0000000079703fff] usable         [    0.000000] BIOS-e820: [mem 0x0000000079704000-0x000000007a003fff] reserved         [    0.000000] BIOS-e820: [mem 0x000000007a004000-0x000000007a06bfff] ACPI data         [    0.000000] BIOS-e820: [mem 0x000000007a06c000-0x000000007a073fff] ACPI NVS         [    0.000000] BIOS-e820: [mem 0x000000007a074000-0x000000007fffffff] reserved         [    0.000000] BIOS-e820: [mem 0x00000000ff800000-0x00000000ffffffff] reserved   And SBL log shows the same case:           Call FspSiliconInit ...         Success         MEM: 0000000000000000 00000000000A0000 00 1         MEM: 00000000000A0000 0000000000060000 00 2         MEM: 0000000000100000 000000000FF00000 00 1         MEM: 0000000010000000 0000000002151000 00 2         MEM: 0000000012151000 00000000675B3000 00 1         MEM: 0000000079704000 0000000000900000 01 2         MEM: 000000007A004000 0000000000068000 00 3         MEM: 000000007A06C000 0000000000008000 00 4         MEM: 000000007A074000 0000000000B8C000 00 2         MEM: 000000007AC00000 0000000000400000 00 2         MEM: 000000007B000000 0000000000800000 00 2         MEM: 000000007B800000 0000000004800000 00 2         MEM: 00000000FF800000 0000000000800000 00 2         MP Init (Wakeup)         MP Init (Run)   Actually, there is another DDR memory block (mem 0x0000000100000000-0x000000027fffffff) on the board. Could any one provide some methods to update the SBL Memory Info, please?   -- Sbl-devel mailing list Sbl-devel(a)lists.01.org https://lists.01.org/mailman/listinfo/sbl-devel

Hi Josh, I am sorry to reply you so late. This modification is workable on UP2 board for detecting the whole 8G memory. Thanks, Jerry -----Original Message-----  From: Cofreros Jr, jose SX Date: 2018-12-13 16:48 To: zhou_c@hoperun.com; Park, Aiden; sbl-devel CC: zhou_x1 Subject: RE: [Sbl-devel] How to update Mem info in E820 Table Hi Jerry,   Good day! May I know if you are already able to detect the whole 4GB DDR memory?     With best regards, Josh     -----Original Message----- From: Sbl-devel [mailto:sbl-devel-bounces@lists.01.org] On Behalf Of zhou_c(a)hoperun.com Sent: Thursday, December 6, 2018 11:32 AM To: Park, Aiden <aiden.park(a)intel.com&gt;; sbl-devel <sbl-devel(a)lists.01.org&gt; Cc: zhou_x1 <zhou_x1(a)hoperun.com&gt; Subject: Re: [Sbl-devel] How to update Mem info in E820 Table   Hi Aiden,   Great! This modification is really good for me! Thanks for your help!   Thanks, Jerry Zhou   -----Original Message----- From: Park, Aiden Date: 2018-12-06 11:15 To: zhou_c@hoperun.com; sbl-devel CC: zhou_x1 Subject: RE: RE: [Sbl-devel] How to update Mem info in E820 Table Hi Jerry,   Good to hear that you got increased size. Then, you can change all ChX_RankEnable 0x1 to 0x3. Looking forward to good news.   --- a/Platform/ApollolakeBoardPkg/CfgData/CfgData_Ext_Up2.dlt +++ b/Platform/ApollolakeBoardPkg/CfgData/CfgData_Ext_Up2.dlt @@ -20,20 +20,20 @@ PLATFORMID_CFG_DATA.PlatformId           | 0x000E   PLAT_NAME_CFG_DATA.PlatformName          | 'UP2' -MEMORY_CFG_DATA.DualRankSupportEnable    | 0x0 +MEMORY_CFG_DATA.DualRankSupportEnable    | 0x1 MEMORY_CFG_DATA.RmtMode                  | 0x0 MEMORY_CFG_DATA.MemorySizeLimit          | 0x0 -MEMORY_CFG_DATA.Ch0_RankEnable           | 0x1 +MEMORY_CFG_DATA.Ch0_RankEnable           | 0x3 MEMORY_CFG_DATA.Ch0_DramDensity          | 0x2 -MEMORY_CFG_DATA.Ch1_RankEnable           | 0x1 +MEMORY_CFG_DATA.Ch1_RankEnable           | 0x3 MEMORY_CFG_DATA.Ch1_DramDensity          | 0x2 -MEMORY_CFG_DATA.Ch2_RankEnable           | 0x0 +MEMORY_CFG_DATA.Ch2_RankEnable           | 0x3 MEMORY_CFG_DATA.Ch2_DramDensity          | 0x2 -MEMORY_CFG_DATA.Ch3_RankEnable           | 0x0 +MEMORY_CFG_DATA.Ch3_RankEnable           | 0x3 MEMORY_CFG_DATA.Ch3_DramDensity          | 0x2 MEMORY_CFG_DATA.RmtCheckRun              | 0x3   Best Regards, Aiden   -----Original Message----- From: zhou_c(a)hoperun.com [mailto:zhou_c@hoperun.com] Sent: Wednesday, December 5, 2018 6:25 PM To: Park, Aiden <aiden.park(a)intel.com&gt;; sbl-devel <sbl-devel(a)lists.01.org&gt; Cc: zhou_x1 <zhou_x1(a)hoperun.com&gt; Subject: Re: RE: [Sbl-devel] How to update Mem info in E820 Table   Hi Aiden,   Thanks for your reply. My memory size increase to 4G from 2G after applying your patch. Could your provide some more help to us for detecting whole DDR memory [8G]? And what necessary information do you need?   Thanks, Jerry Zhou   From: Park, Aiden Date: 2018-12-06 08:56 To: zhou_c@hoperun.com; sbl-devel CC: zhou_x1 Subject: RE: [Sbl-devel] How to update Mem info in E820 Table Hello,   Thanks for letting us know this issue. Unfortunately, I only have 2GB UP2 board, so I can just tell you to modify some memory configuration parameters as below. I hope this would help your issue.   --- a/Platform/ApollolakeBoardPkg/CfgData/CfgData_Ext_Up2.dlt +++ b/Platform/ApollolakeBoardPkg/CfgData/CfgData_Ext_Up2.dlt @@ -20,20 +20,20 @@ PLATFORMID_CFG_DATA.PlatformId           | 0x000E   PLAT_NAME_CFG_DATA.PlatformName          | 'UP2' -MEMORY_CFG_DATA.DualRankSupportEnable    | 0x0 +MEMORY_CFG_DATA.DualRankSupportEnable    | 0x1 MEMORY_CFG_DATA.RmtMode                  | 0x0 MEMORY_CFG_DATA.MemorySizeLimit          | 0x0 MEMORY_CFG_DATA.Ch0_RankEnable           | 0x1 MEMORY_CFG_DATA.Ch0_DramDensity          | 0x2 MEMORY_CFG_DATA.Ch1_RankEnable           | 0x1 MEMORY_CFG_DATA.Ch1_DramDensity          | 0x2 -MEMORY_CFG_DATA.Ch2_RankEnable           | 0x0 +MEMORY_CFG_DATA.Ch2_RankEnable           | 0x1 MEMORY_CFG_DATA.Ch2_DramDensity          | 0x2 -MEMORY_CFG_DATA.Ch3_RankEnable           | 0x0 +MEMORY_CFG_DATA.Ch3_RankEnable           | 0x1 MEMORY_CFG_DATA.Ch3_DramDensity          | 0x2 MEMORY_CFG_DATA.RmtCheckRun              | 0x3   Best Regards, Aiden   -----Original Message----- From: Sbl-devel [mailto:sbl-devel-bounces@lists.01.org] On Behalf Of zhou_c(a)hoperun.com Sent: Tuesday, December 4, 2018 10:16 PM To: sbl-devel <sbl-devel(a)lists.01.org&gt; Cc: zhou_x1 <zhou_x1(a)hoperun.com&gt; Subject: [Sbl-devel] How to update Mem info in E820 Table   Hi Guys,   Recently, I got an issue on UP2 boards after deploying latest SBL on it. Linux kernel only got 2G memory. But there is 8G DDR physical memory on board.   After checking dmesg:           [    0.000000] BIOS-e820: [mem 0x0000000000000000-0x000000000008ffff] usable         [    0.000000] BIOS-e820: [mem 0x0000000000090000-0x00000000000fffff] reserved         [    0.000000] BIOS-e820: [mem 0x0000000000100000-0x000000000fffffff] usable         [    0.000000] BIOS-e820: [mem 0x0000000010000000-0x0000000012150fff] reserved         [    0.000000] BIOS-e820: [mem 0x0000000012151000-0x000000006dffffff] usable         [    0.000000] BIOS-e820: [mem 0x0000000072800000-0x0000000079703fff] usable         [    0.000000] BIOS-e820: [mem 0x0000000079704000-0x000000007a003fff] reserved         [    0.000000] BIOS-e820: [mem 0x000000007a004000-0x000000007a06bfff] ACPI data         [    0.000000] BIOS-e820: [mem 0x000000007a06c000-0x000000007a073fff] ACPI NVS         [    0.000000] BIOS-e820: [mem 0x000000007a074000-0x000000007fffffff] reserved         [    0.000000] BIOS-e820: [mem 0x00000000ff800000-0x00000000ffffffff] reserved   And SBL log shows the same case:           Call FspSiliconInit ...         Success         MEM: 0000000000000000 00000000000A0000 00 1         MEM: 00000000000A0000 0000000000060000 00 2         MEM: 0000000000100000 000000000FF00000 00 1         MEM: 0000000010000000 0000000002151000 00 2         MEM: 0000000012151000 00000000675B3000 00 1         MEM: 0000000079704000 0000000000900000 01 2         MEM: 000000007A004000 0000000000068000 00 3         MEM: 000000007A06C000 0000000000008000 00 4         MEM: 000000007A074000 0000000000B8C000 00 2         MEM: 000000007AC00000 0000000000400000 00 2         MEM: 000000007B000000 0000000000800000 00 2         MEM: 000000007B800000 0000000004800000 00 2         MEM: 00000000FF800000 0000000000800000 00 2         MP Init (Wakeup)         MP Init (Run)   Actually, there is another DDR memory block (mem 0x0000000100000000-0x000000027fffffff) on the board. Could any one provide some methods to update the SBL Memory Info, please?   -- Sbl-devel mailing list Sbl-devel(a)lists.01.org https://lists.01.org/mailman/listinfo/sbl-devel -- Sbl-devel mailing list Sbl-devel(a)lists.01.org https://lists.01.org/mailman/listinfo/sbl-devel